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The world of semiconductors is experiencing a golden era of innovation and technological advancements. From autonomous vehicles to 5G, IoT, and AI/ML, the generational drivers are fueling this revolution. With chips becoming ubiquitous in various devices, chip manufacturing companies must keep up with the insatiable demands for high performance, low power requirements, more functionality, and less turnaround time. This is where AI-enabled EDA tools offer improved productivity, better PPA, and the ability to produce many more chips with the same resources. At the forefront of this AI-driven revolution is Cadence, offering a bouquet of AI platforms and EDA tools with AI that are revolutionizing VLSI design.
In this blog, we will explore how to improve PPA and productivity by Leveraging the power of AI-driven design optimizer Cadence Cerebrus. It was presented during the recent CadenceLIVE India 2023. So, fasten your seatbelts for this exciting journey about the Cadence Cerebrus and its apps.
As the world continues to rely more heavily on technology, the demand for faster and more efficient chips only continues to grow. This is where Cadence Cerebrus comes in. This AI-driven tool is changing the game when it comes to VLSI design, optimizing power, performance, and area in synthesis and place and route runs. Gone are the days when multiple engineers were needed to implement each SoC block. With Cadence Cerebrus, one engineer can achieve multiple optimization objectives, making it a scalable solution even for the largest SoCs.
The Cadence Cerebrus Manager, which is responsible for managing the distributed computing and run management, consists of a Reinforcement Learning Engine, which is responsible for making intelligent decisions to meet and beat design objectives. It also comes with a very sophisticated data analytics engine for the user to monitor the runs and make interactive decisions if required. All of the transfer Learning is captured into a Machine learning Model that can then be used for new RTL or netlist drops of the same or similar designs, improving overall turnaround time for design closure significantly. Along with the fundamental optimization of baseline flow by using tool settings and improved flow recipes, this AI-enabled platform comes with a comprehensive suite of Cadence Cerebrus Apps that can be used individually or in conjunction with the fundamental Cadence Cerebrus to provide Pareto optimal solution for the design. Below, we will be talking in depth regarding various apps, but one thing to keep in mind is that users can also define their own apps and provide to the system for costing to improve optimization as desired. Within the Cadence Cerebrus tool, multiple apps can be developed to optimize PPA. The power of Cadence Cerebrus lies in its ability to perform multi-engine, multi-run tasks, often called PPA sweeps, to achieve significant productivity improvements. With Cadence Cerebrus, tape-outs can be completed almost 10X faster than traditional methods. The results of these apps can then be reused in a full PPA. Few of these apps are
FP-Opt can evaluate multiple floorplans, including BBOX resizing (shrink, expand, aspect ratio changes) and macro placements. It uses the existing “base” floorplan + flow to generate full-flow results for QOR comparison and costing. Floorplan and Flow PPA optimization can be done concurrently. Alternatively, the best floorplans can be selected, and then Flow PPA Opt can be run on them. FP-Opt can be extended to include user primitives that vary power grid density, different regions/domain placements, etc. FP-Opt can also be used for concurrent macro placement (CMP) without resizing the floorplan. By default, it explores global placement and optimization parameters to influence macro and standard-cell placement.
The complexities involved in introducing multiple voltage libraries with varying performance levels at different stages of the design process. However, with the advent of AI-powered solutions like the VT Opt app, designers can now optimize their designs more efficiently and effectively.
Cadence Cerebrus allows you to use the VT Optimizer app to tune a multi-VT flow, which enhances the PPA. Cadence Cerebrus creates various full-flow VT recipes to be used by the VT Optimizer app by allowing or restricting various selective VT types across the flow stages. The VT Opt app explores the solution space to determine which libraries should be introduced at which stage to achieve the best possible performance in terms of power, leakage, and dynamic performance while minimizing overall costs. To achieve even better results, the VT Opt app can be used in conjunction with the PPA app. This powerful combination can provide designers with the optimal library mix for each block and design, simplifying the design process and reducing overall costs.
Use the Clock App to tune the common Clock Tree Synthesis (CTS) settings and explore flexH opportunities to enhance PPA. It has the following two main components:
By experimenting with different variables, such as congestion management and power effort during clock synthesis, you can determine the best recipe for your design. The Clock Tree Optimization (CTS Opt) feature allows for experimentation with various Flex Tree topologies, including source point, taps, buffer, and whether to use a homogeneous or heterogeneous FlexH tree. The app allows you to factor in all costs, and it provides the benefits of different experiments and their impact on design, making it easier to find the best scenario.
Most devices have multiple Operating Points with different Voltage / Frequency Specs. Obtaining the optimal combination of Voltage/Frequency points for operating/optimizing a given design can be challenging. For example, optimizing for Overdrive corner Freq may limit power recovery at Nominal Voltage. The Voltage-Frequency Optimizer enables efficient discovery of the optimal Voltage-Frequency points for best PPA.
PG MESH optimizer, which allows you to experiment with different power grid configurations to maximize your PPA. It's important to assess your design on multiple metrics, including basic PPA, drop limits, and routing convergence, to ensure that any optimizations do not negatively impact the overall project. These tools can be used in different project stages, depending on your goals and requirements. It's also possible to create your parameters and cost mechanisms to build your app or work with developers to create new apps in the future. Cadence Cerebrus is the future of VLSI design. Its AI-driven technology is revolutionizing how we optimize power, performance, and area in synthesis and place and route runs. With its ability to learn and adapt, Cadence Cerebrus offers a unique user experience that makes it a top-of-the-line tool for semiconductor chip design.