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With form factors shrinking and data-intensive endeavors of the upcoming industries like IoT, Robotics, Self-Driving Cars, 5G, and 6G phones, designs are getting more complex. There are many challenges like congestion, routing, on-chip variations, and unconstrained paths that must be addressed.
Resolving congestion or local hot spots seen after placement by efficient schemes and rapid adoption kits (RAKs) can be used to quickly learn about the recent technologies and resolve issues. The best practices are captured in RAKs and serve as ready solutions to the customers. There are methodology articles with advanced solutions at the Cadence Support portal site, it has collated years of experience of experts to provide tips and techniques to help meet your design PPA and TAT requirements. The resource is available 24X7.
These challenges and their mitigation using Cadence support are the talks of this blog.
With the shrinking cell dimensions and industry inclination towards reducing metal layers available for routing, the congestion is increasing. Major reasons for routing congestion are as under:
Congestion is very critical for any design and can be mitigated by following the below settings:
Track opt-based routing helps in reducing the timing jump between pre-route and post-route, and thus enables faster design closure.
Clocks consume 30-40% of the total power consumption, the schemes such as Mesh, conventional H-tree has a higher QoR (quality of results) than normal CTS, but there are concerns such as low degree of freedom in a clock tree design, man-hours for creation, and high-power consumption. The traditional schemes that use Slack, skew minimization, and performing CTS separately suffer from a timing gap between ideal clocks used pre-CTS and propagated clocks post-CTS.
Flexible H-tree CTS, which overcomes the disadvantages of the low degree of freedom in clock tree design while maintaining the advantages of the conventional H-tree. Cadence, Flexible - H helps to find the best compromise between avoiding blockages and power rails, adhering to partition, module, and power domain constraints, and optimizing insertion delay, power, and skew.
Clock concurrent optimization (CCOpt) helps in merging CTS with the physical optimization, so CTS is timing window driven rather than skew drive. The Innovus Implementation system features flexible 2D/3D congestion mode, the Early Global Route (eGR) brings further improvements in total negative slack (TNS) and worst negative slack (WNS), along with predictable design closure. There are multiple benefits of using CCopt using Innovus along with excellent CTS such as
The NanoRoute tool also provides a structured router capability that can be used for selective pre-routes, shielding, and high-frequency bus routing.
Traditionally, modeling of the on-chip process variation has been achieved through scaling of the nominal delays of all instances with a single derating factor which is referred to as OCV. It may lead to over-design and an increase in turnaround time for timing closure. Another way to model variability accurately is to use statistical static timing analysis (SSTA) which is much more accurate but is much more expensive in terms of run time and memory and requires special timing libraries. Statistical OCV (SOCV) provides a good compromise between the run time and accuracy for modeling variation by overcoming challenges related to OCV and SSTA.
Statistical OCV (SOCV) is a new analysis technique that provides for a good compromise between the run time and accuracy for modelling variation by overcoming challenges related to OCV and SSTA. SOCV computes the impact of local process variations on the delay and slew of each instance in the design at a given global variation corner. SOCV uses only a single parameter to model variation and reduces the complexity. The main features of SOCV are
It provides a variety of solutions to on-chip variation (OCV) issues and debugging. With the reducing chip size, OCV becomes a critical issue as it makes a considerable impact on timing, so some cells may run fast/slow depending on process variation. A design is said to have met the timing constraints if it passes through both slow corner and fast corner timing analysis. As we move to lower geometry nodes, increased users are adopting SOCV analysis to reduce pessimism. This SOCV debugging RAK provides a variety of SOCV related problems, solutions, and the debugging approach for users to take care of most of the problems they are facing related to SOCV analysis using Cadence Tempus Timing Signoff Analysis Solution. It helps in faster debugging of SOCV related issues, including investigating various timing analysis problems, reporting SOCV timing results, performing SOCV timing calculations, etc.
While performing static timing analysis (STA), designers often come across timing paths that are not analyzed by the STA tool. A path cannot be reported as constrained due to missing or incorrect constraints, path exceptions, timing-library-related issues, and so on. However, for optimal placements and best fitting results, it is highly recommended that all paths and ports be constrained. There are various approaches to debug the reason for a path not reported as a constrained timing path, sometimes it becomes challenging for the designer to debug the reason for the path to be not reported as a constrained path. A single debugging approach may not be applicable in all the scenarios.
Unconstrained path debugging RAK covers a comprehensive document and a lab covering various situations where a path will not be reported as a constrained path. Further, this document covers a flow-chart to explain the debugging approach to be adopted based on the observations at each stage to conclude the reason for the path not reporting as a constrained path.
Cadence Tempus solution tackles the most advanced challenges in meeting the timing constraints, such as full signal integrity (SI) analysis, glitch analysis and propagation, statistical on-chip variation (SOCV), multi-mode and multi-corner (MMMC) analysis, static and dynamic power reduction, and hierarchical timing models. Tempus offers to reduce the unwarranted pessimism caused by on-chip variation. Tempus solution can also accurately model and calculate the ultra-low voltage effects at 7nm and below that cause the statistical variation to be non-symmetrically skewed about the mean (third moment).
Congestion is always a bottleneck in the designs, so analyzing the design early would help in faster design closure. Various flow tweaks by designers help in design convergence while meeting PPA goals. Various flow tweaks help in design convergence while meeting PPA goals. CTS recipe/flex Htree CTS recipe helps achieve efficient all corner hold closure together with skew and ID reduction. As we move to lower geometry nodes, more users are adopting SOCV analysis to reduce pessimism. The SOCV debugging RAK provides a variety of SOCV related problems, solutions, and the debugging approach for users.