Patterns, a Unified Language between Design and Manufacturing

There will be no design without manufacturing and manufacturing is mainly about patterns and patterning. Without proper transfer of the design patterns to silicon, there would be no semiconductor product. So, it’s with no surprise that several papers on pattern analysis have been selected in the DTCO session of the SPIE Advanced Lithography conference. In this session, you will find 3 papers, co-authored with Cadence, which cover a wide range of applications based on advanced pattern analysis. I find it interesting that each of these papers covers one essential step of the design to manufacturing flow: design signoff, mask data preparation and failure analysis.

The first paper is about hotspot prediction at signoff. In collaboration with the Hong-Kong University, Cadence will present a yield improvement application based on Squish-net, the new Cadence machine learning solution dedicated to pattern analysis. Unlike other hotspot prediction based on machine learning which suffer from inefficient data storage (e.g. images), or information loss (e.g. density-based feature, and CCS), Squish-Net is a convolutional neural network where the input pattern is encoded in squish representation, resulting in high data compression with no information loss. In this flow, the machine learning prediction stage is combined with the pattern cataloging and pattern matching steps for full-chip level layout verification and demonstrated a 98.89% accuracy in predicting hotspot labeled patterns on the ICCAD 2012 benchmark.  For more information about this collaboration, attend this session “Hotspot Detection Using Squish-Net” on Thursday, Feb. 28. 1:30 – 3:30

Strong from their past collaboration on machine-learning based hotspot prediction, Cadence and Samsung teamed up again to address, this time, the fixing of these hotspots and the general improvement of layout quality prior to mask data prep. A full-chip pattern-based layout optimization to improve the robustness and process window of weak spots and add via redundancy prior to mask data prep. This solution applied to 7nm designs achieved 9.1%-41% redundant-via-rate improvements. This pattern-based replacement for design manufacturability improvement is also based on the squish representation. It is applied prior to mask data preparation but can be easily extended to in-design layout optimization.  For more information about this collaboration, attend this session “A Novel Design-for-Yield Solution Based on Interconnect-Level Layout Improvements at 7nm Technology Node” on Wednesday, Feb. 27. 8:00 a.m. – 10:00 a.m.

Despite all the effort to predict and prevent hotspots, failures may still happen and root cause analysis (RCA) is very time-consuming and costly. AMD will present a pattern-aware diagnostics solution to accelerate defect root cause identification developed with Cadence. Using the high-performance Cadence pattern cataloging and powerful Squish representation, a library of scored patterns from multiple established full-chip designs is built and then compared to the patterns interacting with nets reported in diagnosis callouts. All these patterns of interest (POIs) are then further analyzed to identify the features of interest (FOIs), augmented with the volume diagnosis results identifying nets with likely open or short defects, and exported as a dataframe. This dataframe is then processed by conventional machine learning techniques to identify likely root cause(s) for failures and suggest refined failure locations for targeted inspection, physical failure analysis, or other electrical failure analysis.  For more information about this solution, attend the session “Pattern-Aware Diagnostics: Using High-Performance Pattern Analysis to Identify Defect Root Cause” on Wednesday, Feb. 27. 10:30 a.m. – 12:10 p.m.

Please join us at SPIE for these exciting presentations and learn more about Cadence DFM and lithography solutions February 26 and 27 at booth 213 in Exhibition Hall 1. Cadence will also hold private customer meetings. Check out our event page to learn more and register today by visiting the SPIE Advanced Lithography website.

We hope to see you in San Jose for SPIE Advanced Lithography's 44th year!