Race to First-Pass RTL: Improve PPA Targets Using Stratus HLS

Traditional RTL design methodologies often fall short in the race to deliver faster, more efficient, and power-optimized hardware. They are time-consuming, error-prone, and rigid in architectural exploration. Stratus High-Level Synthesis (HLS) is a proprietary tool of Cadence, a transformative tool that empowers hardware designers to generate synthesizable Verilog RTL from SystemC, transaction-level SystemC, or C++ descriptions. Whether you're a design engineer, verification specialist, or system architect, this post will guide you through the core capabilities of Stratus HLS and how it streamlines, enables smarter, faster, and more optimized hardware development.

Why Stratus HLS?

Stratus HLS is designed to bridge the gap between algorithmic modeling and RTL implementation, delivering easier design re-use and superior PPA in less time. It allows designers to focus on functionality and architecture rather than managing low-level implementation details, and the capability to manage and automate the design process. Few real-world case-study statistics showed close to 70% improvement in area, 90% improvement in power, and 100X improvement in overall design time with the use of Stratus HLS-generated Verilog RTL compared with hand-coded Verilog RTL.

Stratus HLS offers numerous benefits to improve design workflow, such as:

• Unified Verification: Use the same testbench across behavioral, RTL, and gate-level simulations.
• Faster Time to RTL: Rapidly iterate through architectural options using synthesis directives and attributes and develop more optimal micro-architectures that deliver greater performance and consume less power.
• Design Space Exploration: Evaluate tradeoffs in area, power, and performance with minimal code changes and enhance the overall design quality.
• Integration with EDA Tools: Seamless handoff to Genus Solutions for running logic synthesis and Joules for performing power estimation and other third-party tools.

What Does Stratus HLS Do?

Stratus HLS transforms untimed SystemC/C++ model descriptions into optimized Verilog RTL through a multi-stage process as listed:

1. Normalization – Parses and prepares the high-level code.
2. Optimization – Builds a control/data flow graph (CDFG) and applies transformations.
3. Scheduling – Maps operations to clock cycles based on constraints.
4. Allocation – Binds operations to hardware resources and generates RTL

Key topics and features of Stratus HLS include:

• Language Constructs: The input language primarily used for Stratus HLS input is SystemC constructs, which provide flexibility and control over your design needs.
• Communication Libraries: P2P and Flex channel libraries are introduced for modular designs and protocol-accurate modeling.
• Pipelining, Latency, and Timing Control: Use timing sweeps to apply synthesis directives and explore trade-offs between area, power, and performance.
• Data Path Optimization: Learn how to automate datapath creation with appropriate synthesis directives or manually define regions to improve synthesis runtime and enable reuse of complex logic blocks.
• Exploration: By exploring hundreds of micro-architectures using automated exploration and optimization techniques, designers can quickly find the most optimal implementation.
• Low-Power Techniques: Optimize clock gating, FSM design, and memory access patterns to measure power using integrated tools and perform power estimates.
• ECO Support: This provides the capability to perform the Engineering Change Order (ECO) in a top-down fashion using the Stratus features or bottom-up fashion by correlating the generated Verilog RTL and the SystemC code.
• Tool Integrations: Stratus HLS seamlessly integrates with other Cadence and third-party tools, enabling a smooth and cohesive design flow from high-level synthesis to implementation. Some notable tool integrations that can be enabled are Xcelium for functional simulation, Genus Synthesis Solution for logic synthesis, and Joules for performing power estimations.

• Other Integrations: Stratus HLS also comprises integrations for:
  • Coverage Checks – Integrated with Cadence Integrated Metrics Center (IMC) to analyze code coverage for SystemC source and Stratus HLS-generated Verilog RTL, and integration of Jasper Unreachability UNR to check for unreachable code in generated RTL.
  • Equivalence Checks – Integrated with CadenceConformal Equivalence Checker to compare Stratus HLS-generated Verilog RTL to the gate-level netlist from logic synthesis.
  • Formal Linting Checks – Integrated with Cadence Jasper Superlint, which performs auto-formal linting checks on Stratus-generated RTL and creates a code analysis report.
• FPGA Synthesis Tool Support: A Stratus HLS behavioral synthesis project intended for an ASIC target can produce RTL targeted to a specific FPGA by modifying the SystemC source code and executing FPGA logic synthesis on that RTL.
• Debug Capabilities: Stratus HLS supports Xcelium and Verisium Debug tools, which facilitate multiple ways of debugging the design, including setting breakpoints, stepping through the design, and viewing the call stack of program execution. Stratus HLS relies on external tools for viewing waveforms, but fully integrates their use into the flow. Logging can be done using the VCD (value change dump), SHM (shared memory), or FSDB (fast signal database) waveform format, and viewed using SimVision and other third-party waveform viewers.

Conclusion

Stratus HLS is more than just a high-level synthesis tool—it's a platform for architectural innovation. Abstracting away low-level RTL coding and enabling rapid design space exploration empowers engineers to focus on what truly matters: building efficient, accurate, scalable, and high-performance hardware. Whether you're designing algorithms, such as codecs, FFTs, and filters, or optimizing a neural network accelerator, developing a signal processing pipeline, Stratus HLS provides the features and flexibility to bring your ideas to silicon faster and smarter.

Training

The Stratus High-Level Synthesis (HLS) Basic Training presented is a basic-level training that provides valuable insights into the Stratus HLS tool. To make the most of the Stratus HLS tool, we recommend focusing on the following key aspects during your training:

• Engage in hands-on exercises to practice writing high-level descriptions and generating RTL code using the Stratus HLS Integrated Design Environment [IDE]. This will help reinforce your understanding and build confidence in using the tool.
• Thoroughly assimilate the Stratus High-Level Synthesis (HLS) Basic Training to familiarize yourself with the tool's Integrated Design Environment (IDE), features, commands, and best practices for generating the most optimized design.

The training is available in two versions:

• Live Training [Instructor-Led]: Please contact Cadence Training.
• Online Training [Self-Learning]: Learn more about the online course on the Cadence ASK site.

Customers/learners will be presented with a badge exam after course completion, and upon successfully achieving the grade, the learner will earn a badge.

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Related Resources

• Stratus Learning Center
• What Is Stratus High-Level Synthesis [Stratus-HLS] (Video)
• Behavioral_Design_Workbench_BDW (Video)
• Stratus-HLS Primer Flow (Video)