Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient

Digital designs are reaching 10's of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule.   A major stumbling block that can be a real threat to that predictability is iterations between different stages of the design flow. There are multiple reasons why this happens but one that should not happen is because you have two design stages giving you two different answers with the same set of data.

The most common, and likely the most costly, is when your implementation tool disagrees with your signoff analysis or extraction tool. At this late stage in the design flow, fixes are costly and time consuming. Also, how do you know which is right? Did your implementation tool miss something or is your signoff tool too pessimistic?

Adding margin to your implementation tool for timing or power is one way to mitigate this problem but this can be costly in several ways:

• Degrades chip performance when timing margins are already tight
• Area and power consumption will increase
• Makes your optimization work longer and harder to close timing - major productivity killer

The easy way around this dilemma is leverage high-precision tools which use the signoff analysis and extraction engines to drive implementation. This way your analysis results are consistent and convergent throughout the flow and you don't get any surprises at the end during signoff. You can essentially catch problems early in the design process which makes them much easier to fix.

It's for this exact reason that Cadence has integrated our signoff analysis and extraction technologies into our implementation environment. Our production proven signoff technologies - Encounter Power System for power analysis, Encounter Timing System for timing and signal integrity, and QRC for digital extraction are built-in the Encounter Digital Implementation (EDI) System. Since we've done this, our users have seen some major productivity benefits when using the complete solution.

A bonus is that, with this integration, you can also signoff during implementation if you like without going to a separate signoff tool. In fact, we have many customers doing just that at 65nm and above where the number of timing and power runs for signoff are much less. This eliminates the need to re-run your timing and power analysis in a different session or tool. Also, it allows the implementation environment to take immediate advantage of the latest analysis capabilities such as advanced OCV, statistical timing, thermal analysis, technology files, etc. to fix design problems instead of just finding them.

You may be wondering... will this slow me down if I'm using signoff engines at every stage? Actually, in this case an ounce of prevention saves you a ton of iterations. And, with the latest developments in mult-CPU performance and capacity of our analysis and extraction solutions, the flow stages are actually much faster.

In short, you should always be doing implementation with signoff in mind so there are no surprises.  Signoff-driven implementation = consistent & convergent = predictable & efficient

Mike Jacobs