SSV 21.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 21.1 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 21.1 release, see the README.txt file in the installation hierarchy.

SSV211

Here is a list of some of the important updates made to Tempus^TM Timing Signoff Solution and Voltus^TM IC Power Integrity Solution for the 21.1 production release:  

Tempus

• New Tempus Licenses
  The following new licenses have been added in Tempus:
  
  • 3nm option: Tempus Timing Signoff Solution 3nm Option
  • Advanced Analysis option: Tempus Advanced Analysis Option
  For detailed information about Tempus licenses, refer to Tempus User Guide on Cadence Support portal.
  
  
• Set Instance Library Flow
  The Tempus software has been enhanced to support instance-level library assignments. With this new flow, the software binds the user-specified library to instances, and overrides the tool’s default library binding mechanism. You can revert to default library binding by using the corresponding reset command.
  For detailed information about the Set Instance Library flow, refer to Tempus User Guide on Cadence Support portal.

For more details about the new and enhanced features introduced in this release, see Tempus What's New.

Voltus

• Extreme Modeling Flow Enhanced
  The Extreme Modeling (XM) flow has been improved to generate context-independent power-grid view (xPGV) models. This flow has the ability to dynamically create xPGV models for only those IP blocks of the design that a user wants to analyze.
  The key capabilities of the new XM model are:
  • accurately capture chip-level RC parasitics and demand current
  • run your largest designs much faster with lower memory
  • reuse IP models in different designs or for multiple instantiations within a design
  For detailed information about Voltus-XM, refer to Voltus User Guide on Cadence Support portal.
  
  
• Support for User-Defined Power Targets
  The State-Propagation-Based Vectorless flow now supports specification of user-defined power targets for full-chip power analysis in the XP mode. You can specify the power targets for full chip, physical block, logical block, and power net. When these targets are specified, Voltus will automatically scale the toggle rates of clock gate ratio, input, macro, and sequential activities to meet the specified power targets.
  For detailed information about the State-Propagation-Based Vectorless flow, refer to Voltus User Guide on Cadence Support portal.
  
  
• New Command to Trim Cell Libraries
  A new command, trim_pg_library, has been added that enables you to remove a cell or a list of cells from a cell library. This command allows you to trim the size of a cell library by removing unwanted cells, which can reduce the overall time required for extraction.
  For detailed information about the trim_pg_library command, refer to Voltus Text Command Reference on Cadence Support portal.
  
  
• Ability to Display Temperature Maps in GUI
  Voltus GUI has been enhanced to display hierarchical temperature maps using the configuration file and the hierarchical layer-based temperature files generated by Celsius^TM (system-level thermal analysis tool). When these files are specified, you can view the tile-based temperature distribution for each layer of the chip.
  For detailed information, refer to the Voltus What's New document on Cadence Support portal.
  

For more details about the new and enhanced features introduced in this release, see Voltus What's New.

Please send questions and feedback to ssv_rm@cadence.com.

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