SSV 23.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 23.1 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 23.1 release, see the README.txt file in the installation hierarchy.

SSV231

Here is a list of some of the important updates made to Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution for the 23.1 production release:

Release-Level Changes

Cadence Doc Assistant—A New Cloud-Based Help System

Starting with this release, a new cloud-based help system, Doc Assistant, has been introduced. Doc Assistant operates in two modes: Online, in which content is accessed from the cloud, and Offline, where documents are stored in the installation directory. Offline mode provides content access even when you are not connected to the internet, while Online mode provides constant access to the latest version of the product documentation.

For more information about Doc Assistant, you can watch the video ‘Cadence Doc Assistant’.

Tempus

• VT Skew Robustness: Tempus introduces the VT skew robustness capability that provides a more accurate means of modeling variation on designs employing multiple VT class libraries (for example, SVT, LVT, and ULVT). Due to variations in the manufacturing process, the voltage threshold (Vth) of a given Vth class may also express variation, resulting in cells of that class operating either faster or slower than the nominal value. Using VT skew robustness, the design engineer can define VT classes and their associated fast and slow derates. VT skew robustness then performs an intelligently enumerated series of analyses to determine the worst-case slack based on the launch and capture path compositions. This advanced approach reduces pessimism compared to traditional STA signoff methodologies.
• Silicon Prediction: Tempus now supports the silicon prediction feature that provides rapid feedback on the silicon device models, libraries, and target device models, allowing you to make quicker adjustments to designs. You can leverage the silicon prediction capability to establish model-to-hardware correlations, achieving desired silicon performance. Silicon prediction is supported across various stages, including Path-Based Analysis (PBA), Graph-Based Analysis (GBA), Tempus Timing Solution, Tempus ECO, and Innovus Implementation System. Additionally, it delivers precise statistical modeling for identifying discrete parameters of silicon variations in pre-silicon signoff STA within the Tempus Timing and Liberate Characterization flow. This enables you to achieve true signoff and optimization, predict timing, and improve PPA and timing yield predictions.
• GUI Added for Customizing Timing Reports: Use the new Report Detail Timing form to generate timing reports based on specified criteria or parameters, such as reports for hold and setup checks or for paths with slack less than the specified value. The form allows you to focus on relevant timing violations to make informed decisions about design modifications.

For more details about the new and enhanced features introduced in this release, see Tempus What's New.

Voltus

• Hyperscale Power Analysis Solution: The Voltus Power Analysis engine now supports distributed architecture for the reduction of linear memory and run-time in hyperscale applications. In this flow, the top-level design is divided into physical tiles. These tiles are further grouped to ensure that a group or partition has the same instance count. Each partition is processed as a separate job so that each distributed job works on similar workloads, as opposed to some jobs doing all the work while others are in the idle state.
• Chip-Centric Thermal Analysis for the Voltus-XP Flow: The chip-centric thermal analysis flow now allows you to perform thermal analysis quickly with the die’s 6 surface temperature boundary conditions and the Voltus Thermal Model (VTM). Using this information, Voltus invokes Celsius to run a thermal analysis to get the temperature distribution inside the chip. The flow has the following benefits:
  • Allows you to run multiple different boundary temperature conditions in sequence to get different chip-centric thermal analysis results. This fast method of thermal simulation can help run more analyses and make better design decisions before tapeout.
  • Enables you to generate different merged top VTMs from the block-level VTMs placed at different locations. The thermal analysis results from these merged VTMs are then used to identify ideal block placement in the early chip floorplan stage.
    
• Die Model Grid Reduction: A new parameter, -grid_reduction_cut_layer parameter has been added to the create_die_model command to specify a cut via layer below which all the layers will be reduced. This feature minimizes data and enables efficient die model generation.
  
• New Unified Power Switch Flow: Voltus introduces a new flow for the analysis of the always-on and switch nets to support the handling of the switch net designs. In this flow, the power-up and always-on analyses are performed in a single flow, during which the switch nets and always-on nets are simulated together resulting in improved performance and accuracy. Previously, the power-up and always-on analyses were performed in separate flows resulting in different circuit structures.
  
• Support to Check the Quality of the Mapping File: The map_dies command has been enhanced to check the quality of the mapping file that gets generated based on the design stack configuration file and die PLOC files. The command now lets you check for any unmatched die-to-die bump mapping, unmapped non-real voltage source bumps, power/ground shorts, and bump map alignment issues between the interposer and logic dies.

For more details about the new and enhanced features introduced in this release, see Voltus What's New.

Please send questions and feedback to ssv_rm@cadence.com.

SSV Release Team