Silicon Signoff and Verification 25.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 25.1 release is now available for download at Cadence Downloads. 

SSV251

Here is a list of some of the important updates made to Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution for the 25.1 production release:

Tempus

• Advanced Multi-Input Switching (AMIS) Analysis: The Tempus software now supports advanced multi-input switching (AMIS) analysis. The AMIS analysis can be used in the case of tied-inputs, or inputs switching independently, which can help to address the inaccuracy and pessimism of the derate-based methodology. The Tempus delay-calculation engine supports advanced MIS natively. The advanced MIS is supported in both GBA and PBA modes.
• Voltage threshold skew modeling and analysis: The Tempus software has been enhanced to analyze the effects of voltage threshold (VT) skew in a multi-VT environment. Due to variations in the manufacturing process, the voltage threshold (Vth) of a given Vth class (e.g., SVT, LVT, ULVT) can show some variations that might result in cells of that class operating either faster or slower than the nominal value. Tempus now supports timing analysis that considers the effects of the Vth skew. The Tempus Vth skew analysis automates the process of selecting the Vth permutations that need to be run, which ensures a robust analysis and optimizes the software to run faster and efficiently.
• Inter-Power Domain (IPD) logic checks: Tempus provides an automated way of checking the sanity of IPD implementation to ensure completeness, thereby reducing the design cycle time and computations required for undesirable inter-power domain (IPD) crossings in a design. The Tempus IPD analysis feature runs diagnostics on all the IPD paths and filters out those paths on which checks need to be performed. The concise diagnostic reports present all the details in a simplified format and provide a complete overview of the IPD implementation in a design. 
• Design Robustness Analysis (DRA): Tempus supports Design Robustness Analysis (DRA) that calculates the probability of an entire chip meeting timing requirements, instead of relying on the probabilities on individual paths to compute the robustness of a chip. The statistical measure of timing slack for the whole design can also be reported.
• Cell EM analysis: The process of electromigration (EM) can drastically reduce the lifetime of a chip by increasing the resistivity of a metal wire or creating a short circuit between adjacent lines. In addition to the effect of electromigration, the material migration process that occurs in electrical devices and interconnects has a significant impact during the IC design and development phase. The Tempus software now supports the cell electromigration constructs that are used in static timing analysis (STA) and ECO flow, which can help to analyze designs, prevent violations, and prepare a robust design with better reliability.
  
• Performance and memory improvements: To enhance user experience, the following performance and memory improvements have been made in Tempus:
  • Overall runtime for large and complex designs using the DSTA master/client architecture has improved by 30%.
  • Memory usage for STA and DSTA clients has improved by 20%. Furthermore, DSTA manager’s memory usage has been saved by 30%.
  • Reading design constraints:
    • Overall turnaround time has improved by up to 4.5x using advanced algorithms and parallel processing techniques.
    • Supports the multi-threaded architecture for processing multiple path exceptions.
    • Incorporates algorithms for efficient exception merging. This consolidates exceptions, ensuring an accurate set of constraints is applied, thus streamlining the timing analysis process.
    • New parallel property fetching mechanism enables the software to retrieve the property details (such as cell delays or physical attributes) concurrently, vastly speeding up data access.
    • Provides optimal timing updates where the software identifies only the affected paths and incrementally updates their timing.

For more details about the new and enhanced features introduced in this release, see Tempus User Guide.

Certus

• Performance and memory enhancements: The following improvements have been made to enhance performance, optimize memory usage, and provide a better user experience for handling large and complex designs:
  • Support for localized disk data caching to retrieve information quickly and speed up the processing time.
  • Enhanced algorithms for saving memory and runtime during setup, hold, and power optimizations.
  • Improved communication between Certus Manager and Certus Clients.
  • Advanced filtering of sub-optimal ECOs.
  • Better handling of Multi-Instantiated Module (MIM) partitions.
  • Improved turnaround time for setup timing closure, Hold timing closure, and power optimization.
  • Support for multi-threading architecture by maximizing resource utilization.
    
• Support for manual ECO: The Certus software now supports the Manual ECO flow to fix timing, functional or design rule violations in a design after the signoff stages. The non-interactive and interactive modes in Manual ECO perform an automatic netlist sync-up of Certus manager, Certus clients, and Tempus clients. Manual ECO implementation is especially useful in critical design phases, enabling precise and quick fixes, thus minimizing design turnaround time before final signoff.
  For detailed information about Manual ECO, see Certus User Guide
  
• 3D-IC timing closure with Certus: An increase in the number of signoff corners in a 3D-IC design presents significant challenges for designers. This has impacted systems utilizing heterogeneous integration, where components (die) fabricated with different semiconductor technologies and process nodes are combined. Furthermore, designs characterized by an enormous instance count, where each stacked die includes millions of instances are also affected. To achieve optimal performance and improve PPA (power, performance, and area) of a design, Certus uses the Rapid, Automated Inter-Die Analysis (RAID) technology, which significantly reduces the corner data and turnaround time. The software natively supports heterogeneous technology files through hierarchy and accounts for die assignments and cell detailed placements using the physically-aware mode.

For more details about the new and enhanced features introduced in this release, see Certus What's New.

Voltus

• New AI-driven technology for improving chip power integrity: Voltus InsightAI, the industry’s first generative AI technology for digital design, has been introduced to help you predict IR drop issues early in the design process, discover their root causes, and then resolve those violations efficiently.
  To support this new technology, the following commands have been introduced:
  • get_ir_insight - Performs aggressor IR impact analysis, reports IR drop statistics, supports timing-aware IR drop fixing, and predicts IR drop for ECO changes.
  • set_voltus_insight_mode  - Configures Voltus InsightAI flow settings, including EIV methods, EIV evaluation windows, and instance-specific thresholds.
  • get_voltus_insight_mode - Generates a configuration template based on the loaded design database and power/rail settings.
• Adaptive ramp-up step resolution based on switch net charging: Voltus now dynamically adjusts the voltage step size during power-up analysis based on the wake-up voltage thresholds. During power-up analysis, the tool dynamically refines voltage step resolution based on the charge level of switch nets. When these nets are 70% charged, the step resolution increases by 2X, at 80% charge, it increases by 4X, and at 90% charge, it increases by 8X. This adaptive approach ensures higher accuracy in capturing IR drop and rush current. This improves simulation precision without unnecessary compute overhead.
• Alignment partitioning support for stacked designs: To improve performance in stacked die (3D-IC) designs, the 3D-IC simulation flow now supports aligned partitioning. When multiple dies have regions located at the same (x, y) coordinates, these areas can now be grouped into the same partition. This feature leverages the bump-to-bump mapping relation to calculate the die-to-die relative location. The aligned partitioning feature enables more accurate simulation for designs with a large number of inter-die connections.
• Block power reporting enhanced: You can now generate diverse power analysis reports for specific blocks. With this enhancement, you can view and debug the power consumption issues for a specific block after the power run is complete.
• State-propagation-based vectorless flow improved: The State-Propagation-Based Vectorless flow has been enhanced to support stable scheduling of ICGs and flops. This enablement allows minimal result changes during the ECO stage of the design because only the altered parts of your design will experience changes in the switching activity.
• Ability to merge DDV PGVs: The -merge_ddv_currents parameter has been added to the merge_pg_library command to merge the tap currents from multiple single-voltage DDV PGVs with different voltages to create a single multi-voltage PGV.

For more details about the new and enhanced features introduced in this release, see Voltus What's New.

Please send questions and feedback to ssv_rm@cadence.com.

SSV Release Team