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At 45nm chip designs, manufacturing and process control becomes increasingly difficult. Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. STA compensates for this variability by requiring aggressive guard bands and by using multiple corners or scenarios to reflect different manufacturing conditions.
However, this old fashioned deterministic STA still remains popular amongst mainstream designers and for good reasons:
On the other hand, while STA has been very successful, it still has a number of limitations, which are getting magnified at lower process nodes:
Statistical STA (SSTA) attacks these limitations more or less directly. First, SSTA uses sensitivities to find correlations among delays. Then it uses these correlations when computing how to add statistical distributions of delays. SSTA makes it possible to break through the barriers of corner analysis and holistically model the many factors affecting process variation in a single analysis run. It enables designers to effectively model process and environmental variation, it obviates the need for multiple corners, and it removes much of the inherent pessimism. SSTA allows for reduced guard-banding, which results in decreased area, decreased power consumption, and improved chip performance.
However, some mainstream designers still prefer to sit on the fence and and wait for early adopters to employ SSTA. A number of criticisms are leveled at SSTA:
I would love to hear what you think about SSTA. Feel free to share your experiences and thoughts on traditional STA, process variation/corners and SSTA. And in upcoming blogs, we can explore how SSTA is becoming more of a reality. How the past limitations are being addressed and how it is becoming a useful weapon in the designer's arsenal. Until then...