Test Smarter, Not Harder: Explore Cadence’s Hands-On DFT Training Journey

In today's competitive semiconductor industry, robust testing methodologies are essential for delivering high-quality, reliable chips. Whether you're a designer, verification engineer, or a manager seeking to upskill your team, Cadence's Design for Test (DFT) training series offers a comprehensive learning path. Here's how you can master DFT, from fundamentals to advanced topics like Structural and Functional Testing, Memory BIST, Test Compression, and Diagnostics runs.
Cadence's Modus DFT Software Solution software is a fully integrated suite of tools designed from the beginning to interact and work with each other. It is a complete tool suite supporting all four disciplines:

• DFT Synthesis: The process of inserting test logic into a design to help make it testable.
• Test Verification: The process of identifying the test logic and verifying that it has been inserted and integrated correctly. And identify any design characteristics that will create testing problems.
• Pattern Generation: The process of creating test vectors that are applied by the tester.
• Failure Diagnostics: The process of working backward from failure miscompares to the probable cause and helps in the production and yield management of semiconductor lines.

Design for Test Fundamentals Training

The Design for Test Fundamentals training course provides a comprehensive introduction to the principles and practices of Design for Test (DFT) in Digital Integrated Circuit (IC) design. It is designed for engineers and professionals seeking to understand the critical role of testing in the chip development and manufacturing process. No prerequisites are required, making it accessible to both beginners and those looking to refresh their knowledge. The training offers the following objectives:

• Purpose and Target of Testing: Why testing is essential, what is tested, and the basics of testing methods.
• Testing Methods: Functional vs. structural testing, ATPG (Automatic Test Pattern Generation), scan testing, and test compaction.
• DFT Design Rules: Key rules for scan chain operation, controllable reset and clock, and best practices for high test coverage.
• Advanced Topics: Built-In Self-Test (BIST), test compression, additional tests (IDDQ, I/O wrap, parametric tests).
• Hands-On Lab: Running the synthesis flow with DFT.

After completing the lab training for Design for Test Fundamentals (version 25.1), you will learn the essential steps and practical skills required to implement scan-based Design for Test (DFT) in digital designs using Cadence Genus Synthesis Solution. They will gain hands-on experience running the full synthesis flow with DFT, including loading design files, reading constraints, setting up scan styles, and defining test signals:

• The "Scan_Enable" signal selects regular functional data input or a new scan data input to the flip-flop.
• Scan inputs are chained to the output of other flip-flops.
• Same clocks are used for both scan and functional operation.

Test Synthesis with Genus Stylus Common UI Training

In the Test Synthesis with Genus Stylus Common UI training course, you learn to use Genus Synthesis Solution in Stylus Common UI mode to insert test structures in your design. You learn how to set up constraints for DFT, checking DFT rules, fixing violations, synthesizing the design, and configuring and connecting scan chains. You learn to generate various reports and to interface with other tools. You also explore various troubleshooting scenarios while inserting scan cells in the design. You also learn Hierarchical Scan Synthesis and Advanced DFT logic insertion like PMBIST, Compression, LBIST, OPCG, IEEE 1500 wrapper, etc., in the design.

DFT features in Genus Synthesis Solution include:

• Checking DFT rules for scan chain creation
• Inserting shadow logic around untestable logic
• Creating scan chain abstraction models
• Configuring and connecting scan chains
• Outputting scan DEF and ATPG interface files
• Analyzing logic for testability and inserting test points
• Inserting Boundary Scan
• Inserting PMBIST logic
• Inserting test Compression logic
• Inserting OPCG, 1500 Core Wrapper, LBIST

Upon completing this lab training, students will gain practical, hands-on experience in implementing Design-for-Test (DFT) techniques using Cadence Genus Synthesis Solution. They will learn how to identify and resolve DFT violations, configure and connect scan chains, insert shadow logic around untestable memory blocks, and apply advanced testability features, such as PMBIST, compression, and LBIST. Through step-by-step labs and real-world scripting exercises, students will develop the skills needed to automate DFT flows, troubleshoot scan issues, and generate comprehensive reports to validate their designs.

ATPG Flow with Modus DFT Software Solution Training

The ATPG Flow with Modus DFT Software Solution training course guides you through the complete ATPG (Automatic Test Pattern Generation) flow, beginning with identifying key steps and creating a design image from the required input files, like a netlist. You'll learn to define and create test modes, verify test structures, and construct fault models to detect and locate design issues. From there, you'll dive into hands-on ATPG testing techniques, including dynamic fault tests, scan chain tests, sequential tests, bridging fault tests, and IDDQ tests. Finally, you'll be an expert in writing ATPG vectors to run these tests effectively. By the end of this course, you'll have the skills to design, validate, and optimize test strategies for complex digital systems. In this course, you will learn how to debug the broken scan chains. The course covers various aspects of the software, including its key technologies, ATPG flow, debugging techniques, and test pattern generation.

ATPG Test Pattern Creation Flow

After completing this training, you will be able to:

• Introduce the Modus DFT Software Solution
• Identify the Modus key technologies
• Define the ATPG (Automatic Test Pattern Generation) flow
• Build a test model (building the Modus DFT Software Solution design database)
• Build the fault model
• Build test modes
• Verify test structures (design rule checking)
• Create static tests (Automatic Test Pattern Generation)
• Write the vectors (Verilog, STIL, WGL)
• Debug the broken scan chains using the GUI and Tcl command-line techniques
• Debug the test patterns

After completing the ATPG Flow with Modus v25.1 lab training, students will gain hands-on experience with industry-standard ATPG test patterns and Modus DFT tools, empowering them to confidently tackle real-world digital test challenges. By performing a variety of ATPG tests—including dynamic faults, scan chains, sequential, bridging fault, and IDDQ tests, user will develop a comprehensive understanding of fault coverage and test effectiveness.

Diagnostics with Modus DFT Software Solution Training

The Diagnostics with Modus DFT Software Solution training course is designed to provide participants with comprehensive knowledge and hands-on experience in diagnosing defects in semiconductor devices using the Cadence Modus DFT Software Solution. The course covers converting tester data to the required Chip Pad Pattern (CPP) failure data format, diagnosing single and multiple defects, and scan chain failures. It also includes physical-aware diagnostics using Cadence Virtuoso Physical Layout Viewer and volume diagnostics analysis to address yield problems across large numbers of failing devices. Participants will learn to use various commands and tools within Modus to perform these diagnostics efficiently, ultimately enhancing their expertise and career opportunities through Cadence Certified Digital Badges.

Diagnostics with Cadence's Modus DFT Software is intended to assist in identifying the root causes of defects in manufactured digital semiconductor devices.

There are different types of diagnostic models:

• Basic: Perform diagnosis on a single device to identify logic or scan chain defects
• Physically Aware: Perform diagnosis on a single die to identify logic defects, including bridges and subnet opens
• Physical Analysis: Interactive analysis of defects using the Modus Schematic and Cadence Virtuoso Layout Viewer
• Volume Diagnostics: Perform diagnosis on a large number of failing dies to identify yield limiters

When you enroll in this training, you will be able to:

• Outline the Modus Diagnostics overview
• Identify the different Diagnostic Models
• Diagnose the single and multiple defects in a single device to identify the location and type of faults
• Diagnose the scan chain failures to locate the failed register
• Identify the key features of logic and scan chain diagnosis in Modus DFT Software
• Diagnose the bridge and open defects that are not modeled in traditional fault models
• Perform the Volume Diagnostic analysis
• Review the results of Volume Diagnostic via log (text files) and the Graphic Volume analysis interface

After completing the labs in the Modus Diagnostics training for version 25.1, you will gain hands-on experience with the entire workflow of digital IC failure diagnostics using Cadence Modus DFT Software Solution.

Learn More

Learn more and enroll in Hands-on Cadence's DFT Training Series! Register for the Online Training with the following steps:

1. Log on to Cadence.com with your registered Cadence ID and password.
2. Select Learning from the menu > Online Courses.
3. Search for "ATPG Flow with Modus DFT Software Solution" using the search bar.
4. Select the course and click "Enroll."
5. Explore our Accelerated Learning option for faster skill-building
6. Earn Digital Badges to showcase your expertise to managers and employers