The Truth About Complete DFT Flow: What Most Engineers Miss

Design for Testability is a critical step in achieving high-quality silicon. In this Training Bytes blog, we are going to explore implementing an efficient DFT flow using the Genus Synthesis Solution, covering key concepts such as synthesis with test, scan insertion, test readiness, and preparing your design for ATPG with Modus and for fault diagnostics.

Synthesis with DFT
In this section, we introduce the DFT implementation flow using the Genus Synthesis Solution. These videos focus on preparing your design for test by integrating DFT architectures early in the flow.

• Ever wonder how DFT fits seamlessly into your synthesis flow? Check out our short byte on YouTube titled: A Design with Test Circuit where you can explore your design with test structures.
• Adding test structures in your design requires some Basic DFT Rule Checks. The intent of these checks to ensure the elements put in the scan chains are shifting data properly.
• DFT isn’t just an added step, it is the backbone of test-ready design. To make the design test ready, you need to fix violations; for example, Fixing Asynchronous Set and Reset Pin Violations. You can also run the DFT rule checker and fix the DFT Violations on a Scan-Mapped Design at any stage in the synthesis with DFT Flow.
• To increase the coverage of your design, Insert Test Points Manually during synthesis.
• You can also Insert Shadow Logic Around the Untestable Logic to increase the design’s controllability and observability.
• To access the functional ports of your chip independent of system logic, Insert the Boundary Scan Architecture in your design.
• You can also learn to add other test structures, such as Memory Built-In-Self-Test (MBIST) and Logic Built-In-Self-Test (LBIST). See our YouTube videos: What is MBIST and What is Logic BIST.

ATPG Flow with Modus DFT Software
Once your design is synthesized and includes the test architecture, you can seamlessly handoff to the Cadence Modus DFT Software solution to run the Automatic Test Pattern Generation ATPG flow. See the following steps and embedded links to the respective topics:

• To understand Modus ATPG Flow Steps and its Graphical User Interface, watch the embedded video.
• The first step is creating a Modus model, defined by Build Model. It does this by reading the design netlist and reading the structural library files combining together to create a design image. This model will be used for all further steps in the ATPG flow.
• You can also build the test mode to set up the device for testing, as described in: What Is Test Mode.
• To update the global fault list faults detected in the design, watch the video: What Is the Commit Experiment?
• If you are curious about writing the industry standard test vector, click on the embedded link and watch the video ATPG Vector Generation and Writing the Patterns.
• You can also debug the broken scan chains in your design by Debugging Broken Scan Chains using the Modus GUI or How to Debug Broken Scan Chains using Tcl Interface in Modus DFT?

Diagnostics with Modus DFT Software
Once your test patterns are generated, the real challenge begins—diagnosing manufacturing defects and identifying faults. Modus Diagnostics assists in identifying the root causes of defects in manufactured digital semiconductor devices.

• Identifying the root cause facilitates corrective actions to avoid future defects and improve product yields. The Modus Test Diagnostics Overview is a good resource to start with.
• Because there is no industry standard, failures from Automated Test Equipment (ATE) are reported in a variety of ASCII formats. You can convert your Tester Fail Data to Chip Pad Pattern CPP Format.
• Modus has established a simple input Failure Format Called Chip Pad Pattern (CPP) file.
• Once you Read the Tester Failure Data into binary format, you start diagnosing the failures in your design.
• With Modus diagnostics capabilities, you can Diagnose Single/Multiple Manufacturing Defects in the functional logic of the chip, select all the faults in the logic back cone of the flops, then perform fault simulation and compare the results.
• Modus DFT Software provides a wrapper that allows you to execute all steps, including determining if the failures are on Logic or Scan patterns, in one command. You can get more information by watching this Demo.

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