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Please join me, Cadence Training and Application Engineer Krishna Atreya, for this free technical Training Webinar.
The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus intelligently optimizes the Cadence digital full flow to meet power, performance, and area (PPA) goals in a completely automated way—letting engineers concurrently optimize multiple block flows, which is particularly important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems.
We’ll dive into:
Wednesday, September 27
07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Berlin / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing
To register for the “Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have” webinar, use the REGISTER button below and sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details.
If you don’t have a Cadence Support account, go to Registration Help or Cadence User Registration, and complete the requested information.
For questions and inquiries or issues with registration, reach out to firstname.lastname@example.org
Keep up with the revolution! Join Cadence’s Cerebrus Intelligent Chip Explorer Training and learn how to use Cadence Cerebrus to scale and automate your design, improve your productivity, and much more.
The online class is free for all Cadence customers with a Learning and Support account.
We can also organize this Cadence Cerebrus Intelligent Chip Explorer Training for you as a “Blended” or “Live” training. Please reach out to Cadence Training for further information.
You can also enjoy this video to get a first impression what is waiting for you!
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