VoltusTM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.
In part 1 of this blog series, we outlined the importance of the Voltus Extreme Modeling (XM) flow for fast, accurate, and memory-efficient power signoff when handling extremely large designs. In this post, I’d like to focus on successfully implementing this hierarchical power integrity solution to create xPGV models of your IP blocks. But before we get to it, it’s essential to understand why and how designers can really benefit from this analysis during the full-chip IC design process.
When Does it Make Sense to Use Hierarchical PI Analysis?
Processing large chips in Voltus can require huge machine resources to get through all the steps from reading in all the required design data to extracting the power grid, analyzing the IR drop and ground bounce, generating reports, and saving volumes of data. If you’re ready for signoff and have hundreds of CPUs to throw at it with multi-terabytes of memory on dedicated servers, Voltus can provide a quality signoff analysis in a reasonable period. But what if you don’t have these resources or your design is not quite finished, and you want some quick feedback before proceeding to signoff? In such a scenario, use a hierarchical approach by generating a power-grid view of the blocks in the design that minimizes the RC network without loss of accuracy. Ideal candidates for this scenario are repetitive blocks that are common in neural network and router chip designs or when you’d like to make engineering change order (ECO) updates to design blocks.
Use Case 1
Here’s a use case that shows how you can run a few instances flat with DEF blocks, while the remaining repetitive ones can be run with xPGV blocks:
Use Case 2
Here’s another case that shows how you can make incremental ECO fixes at the top level using the xPGV blocks, and run the flat-level analysis on a need basis or for the final signoff:
For these recurring or large blocks, the resistor reduction would greatly improve server memory resources.
Design Considerations for Optimal XM IR Drop Analysis
So you’ve decided to run EMIR analysis using the Voltus XM flow, but are not sure where to get started with your first XM project? Here are some guidelines that can help.
Create an XM Model in Three Simple Steps
Step1: Rerun Voltus rail analysis with the xPGV configuration file included. The configuration file includes the block information to generate the XM model.
XPGV Configuration File Format
CELL <block_name>CUT_LAYER <cut_via_layer_name>Lef <tech_lef_name block_lef_name>END
Lef <tech_lef_name block_lef_name>
Step2: Specify the generate_xpgv command after the rail analysis command to read in the rail analysis results and generate xPGV.
generate_xpgv -cell block_name -output_dir PGV_directory -state_directory rail_output_directory
Step3: Validate the tap currents. The xPGV will now contain the upper metal layers preserved as you decided in the xPGV config file but now you will need to validate the tap currents. Both dynamic peak and static average waveforms will be stored in the xPGV. You can validate whether they were stored correctly by loading the dynamic current files in the dynamic waveform viewer, and comparing to the .summary file created in the xPGV output directory.
In the viewer, TC_SUM is the tap current (demand current) used for simulation, which is same as the peak current in the .summary file.
You are now ready to use this xPGV at the top level. In the next post of the Voltus XM blog series, we will talk about how to utilize the xPGV models for the user-defined blocks at the top level. With the aim of improving chip design productivity, Cadence has unleashed this valuable solution to help designers fix power integrity problems while they are laying out their Ultra-Big-Data SoC designs.
Voltus IC Power Integrity Solution User Guide
CadenceTECHTALK: Hierarchical PI Analysis of Large Designs with Voltus Solution
For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.
“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.
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