Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Understanding the power consumption of a system on chip (SoC) is a critical part of silicon signoff. Although this has always been a key requirement in the design cycle, the complexity of today's chips—with their dynamic applications and stringent power budget—makes this an imperative aspect of the design process. To serve the needs of a wide variety of energy-saving applications, "More than Moore" is presently trending. This is due to IC miniaturization down to nanoscale levels as well as the packaging of more functionality into these tiny chips. In this blog series, we share methods for designers to verify that the designs meet their power efficiency specifications. This first post of the series is on event-based power analysis, a power estimation technique for accurate analysis even in very large designs.

The Changing Landscape of Power Estimation Techniques

Historically, power analysis in EDA tools has relied on file formats such as TCF that are concise but lack the temporal relationship between signals needed for an accurate analysis. For power-critical applications, design teams rely on time-based vectors such a VCD or FSDB that allow power engines to perform more accurate instantaneous “event-based” power calculation as and when the transient events occur in the vectors. This comes at a cost in terms of runtime and memory, which is further exacerbated with designs and vectors getting bigger and longer in terms of size and duration, respectively.

Introducing Event-Based Power Analysis

Let us use a simple example of an OR gate to explain the methodology and accuracy advantages of event-based power calculation, as opposed to calculating power from TCF. A file format such as TCF will only represent the averaged out activity numbers for each pin of the “OR” gate, which is then used for power calculation. For example, activity for Input1 will be calculated as 4 toggles in "Tns,” for Input2 as 2 toggles in “Tns,” and for Output it will be calculated as 2 toggles in “Tns.” These averaged activity numbers do not represent the temporal relationship between the inputs and outputs as well as the direction (rise/fall) of the toggles leading to loss of accuracy.
In the same scenario, event-based power calculation will calculate the power as a summation of all the events happening from “t1” through “t6.” For example, at “t1” the power is calculated due to “Input1” rising causing the “Output” to rise as well. This is inherently more accurate as it takes into account the relationship between “Input1” and “Output” as well as the direction (rise) of the toggle.

To enable event-based power calculation, Voltus supports a range of formats from standard functional simulators and emulation tools such as Palladium. Besides the time-based vectors, standard inputs such as DEF, SPEF, Liberty, and Timing data are needed to run an accurate analysis.

The event-based power calculation in Voltus can be used to achieve three tasks:
• Accurately compute and analyze the average power of a chip across all the clock cycles
• Analyze time-based power profiles to identify power-hungry cycles.
• Run accurate transient power analysis for peak power cycles and compute peak IR drop.

Handling of Long Simulation Vectors

Employing traditional methods of power analysis and vector processing for event-based power calculation as shown below would require memory-thirsty servers to run through.

To get around this, Voltus uses a segmented approach where all the three steps of annotation, calculation and construction can be done on smaller segments, allowing the flow to run through faster with a much smaller memory footprint.

Implementation Example of a Large HPC Chip at 7nm

For the design example in the following table, an event-based power calculation was performed for CPU core architecture to meet the required performance goals. Power analysis signoff was about 1.25x faster with 7x lesser memory using the segmented approach when running on a single machine with 16CPUs:

Further reduction in the memory footprint can be achieved for analysis on large designs. Designers can seamlessly distribute event-based analysis across multiple servers depending on the number of physical hierarchies in their design. None of these approaches lead to any loss of accuracy. 

In summary, Voltus power analysis offers a comprehensive solution that enables designers to run an accurate event-based power analysis on large vectors and designs without the need for reserving large servers. Voltus provides many such features and capabilities that minimize power consumption while improving energy efficiency of the IC designs.

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

Click Subscribe to visit the Subscription box at the top of the page, where you can submit your email address to receive notifications about our latest Voltus Voice posts.