A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!

“It’s not what it is, it’s about what it can become”
-The Lorax by Dr. Seuss

Have you recently reached out to open your car and received an unexpected shock…zap! There are no financial or health implications if the door handle of your car zaps you, but an Electrostatic Discharge (ESD) zap event can instantly destroy devices worth billions of dollars. Today, we are aware of the destructive nature of ESD in integrated circuits. With the ever-shrinking device geometries and their increasing complexity, susceptibility to ESD damage has only increased in the recent years. Though it lasts less than a microsecond, a discharge to a chip’s pin or bump is of the order of several thousand volts and could be disastrous to its internal circuits. The charge must be ferreted away before the voltage reaches critical levels (and your system goes kaput!). Consequently, a full-chip ESD protection solution for signoff is required.

With the objective of providing an efficient solution for analysis and optimization of ESD protection circuitry and increasing the survivability of the core circuit, the Cadence® Voltus team is offering a robust ESD analysis flow that encompasses a massively parallel architecture for improved memory footprint, performance and scalability. The solution also offers superior usability by providing an intuitive GUI for review of the ESD analysis results.

The new ESD Analysis flow performs a fast resistance and current density check for ESD discharging paths across multiple diodes or clamps. This rule-file-based analysis allows checking of bump-to-clamp (b2c), bump-to-bump (b2b), and clamp-to-clamp (c2c) effective resistance, as well as connectivity of clamps and bumps, current density (EM) during an ESD zap event, and driver/receiver differential voltage analysis for Charged Device Model (CDM).

The Voltus ESD Analysis solution enables easy identification of ESD issues to implement an effective protection scheme through the following key differentiators:

So next time, be sure to use the Voltus ESD analysis solution to clamp high voltages and avoid a zap event!

- Team Voltus

Related Resources

Voltus IC Power Integrity Solution User Guide

• ESD Analysis

For more information on Cadence silicon signoff and verification products and services, visit www.cadence.com.