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We just recently released a training course that we are excited to tell you about.
The course is RTL-to-GDSII Flow.
This course is unique in that it takes a tiny design through a wide variety of Cadence tools so that you can gain some exposure to tools that you may not be familiar with.
You learn how to implement a design from RTL-to-GDSII using Cadence tools. You will start by learning how to code a design in VHDL or Verilog. You will simulate the coded design, followed by design synthesis and optimization. You will then run equivalency checks at different stages of the flow. After synthesizing the design, you will floorplan, and place-and-route the synthesized netlist while meeting timing. You will run gate-level simulation throughout the flow. Finally, you will write out a GDSII file.
If you are affiliated with a university, you can request access to Cadence software, this training course, and all of our training courses via our Cadence Academic Network Program.
Happy Holidays and Happy Learning!