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Heads-up: there is a free technical webinar next Wednesday 11/12 that goes deeper into the topic of combining formal verification with Cadence's planning & management technology to dramatically improve the throughput of proving assertions, and bug hunting in general. In a phrase, this is a new "productivity flow" which my colleague Bin Ju previewed in her segment on formal verification technology.If you would like to attend you can register here:http://www.secure-register.net/flyer.php?id=263GOOD NEWS: Like at last week's in-person techtorial, all are welcome to ask presenter Robert Juliano plenty of questions. Robert is a "Senior Core Competency Technical Leader", which means he's forgotten more about formal, ABV, and low power analysis with formal technology than most of us mortals will ever know! ;-) He is constantly on the road working with customers', so this is a great opportunity to learn about the real world applications and issues at play here. I challenge you to try and stump him!MORE BACKGROUND ON THE TECHNICAL WEBINAR ITSELF:Highlights of the webinar will include:
* Review of performance improvements you can achive by parallelizing the proofs (backed by customer reports of wall clock run times decreasing from days to hours, and from hours down to minutes)
* Tasks that in the past could have only been done by advanced users writing a bunch of home grown scripts is now possible with a GUI, which is marketing speak for we have simplified the process of "Case Splitting" where you can split a large problem into many parts to solve separately and then bring the results back together to increase bug hunting effectiveness
* New GUI "stuff" that also allows users more flexibility when bug hunting and makes it possible to easily run, and to share formal regression output (some of this regards the new ABV + Enterprise Manager integration Bin briefly noted in her talk last week.Again, here is the registration link:http://www.secure-register.net/flyer.php?id=263*** Note ***This is a *technical* webinar, where the presenter will assume a basic understanding of formal property checking and verification. If you are new to formal property checking you may want to consider reviewing:
* Assertion-based verification and debug of RTL block designshttp://www.cadence.com/products/fv/formal_verifier/Pages/default.aspx* Reading some of the many technical papers in the Resource Library:http://www.cadence.com/products/fv/formal_verifier/Pages/resources.aspx* Feel free to contact my colleagues on the Formal & Assertion Based Verification team directly with your questions: newsletter_ifv at cadence dawt com