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While simulating a VHDL design with Incisive Simulator, if an integer overflow is detected, the simulation stops with the following error message:
Error! integer overflowFile: ./test.vhd, line = 13, pos = 11Scope: :$PROCESS_000Time: 10 FS + 0./test.vhd:13 i := i - 1;
Error! integer overflow
File: ./test.vhd, line = 13, pos = 11
Time: 10 FS + 0
./test.vhd:13 i := i - 1;
Incisive is probably the only simulator to report such error condition. The only other popular VHDL simulator was not able to catch/report this condition, when I last faced it. So a user who is not using Incisive Simulator will not be able to know that his design has VHDL integer variables that overflow, which is usually not the real intent.
Ideally, the VHDL code should be fixed this overflow problem, but in many cases the value (integer overflow) of VHDL integer variables is don't care up to certain simulation time or state of simulation. For such cases, the users simply want to ignore this check in Incisive simulator as well.
How to Ignore "Integer Overflow" in Incisive Simulator
The NCVHDL engine in Incisive Enterprise Simulator also allows flexibility to continue running the simulation even when it detects an integer overflow by setting a pre-defined tcl variable - "intovf_severity_level".
The default value of this variable is ERROR, i.e. stop the simulation at integer overflow. The other values of intovf_severity_level are WARNING and IGNORE.
The value of the intovf_severity_level variable can be changed in Simvision GUI. Select Simulation -> Show Variables menu. Select the intovf_severity_level variable and the value associated with this variable. Change the value to IGNORE (or WARNING). The console window echoes the command.
The easiest way to achieve in batch or regression mode is to add "set intovf_severity_level IGNORE" command in a Tcl input file, before the simulation "run" command.