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Since your circuit always runs at low-power, your
verification should too. To get that
"always-on" low-power verification, Incisive Enterprise Simulator (IES) uniquely verifies low-power behaviors
natively. In some cases that can result
in tests that run faster with power analysis on than with power analysis off -
engage the warp engine!
IES introduced the most comprehensive native-compiled, low-power
analysis features in 2007. Using the CPF
power intent information, IES can verify behaviors such as shutdown, standby
(sleep), isolation, state retention, voltage corruption, and power modes. In addition, it can also automatically generate
assertions (SVA or PSL) to check for these behaviors.
When IES simulates these behaviors it does so through its
unique native-compiled engine so that no PLI calls are needed. This enables the warp speed in two ways - it
provides less drag on the RTL engine and enables unique optimizations not
available through PLI. Since PLI is a
generic simulator API, applications that attach through it are subject to
additional run-time checking that slows the engine while the native application
is trusted by the simulator so that it can run faster. That trust goes on to enable warp speed
because the low-power application can instruct IES to not simulate the shutdown
parts of the circuit, during the time that they are shutdown, resulting in less
circuit to run and higher simulator speeds.
For circuits with major blocks shutdown, the result is a simulation that
runs faster with power verification turned on than turned-off. PLI-based applications just can't compete.
While all this speed is nice, pin-pointing your low-power
bugs is even better. IES is also unique
here with low-power debug capabilities in SimVision. Looking at figure 1 you can see how SimVision
marks signals in isolation and power
down modes. It also automatically maps
power related signals into the waveform window and collects all of the power domain
information into a handy sidebar window as shown in figure 2.
SimVision also provides
a power mode window that shows all of the power modes in the chip and shows the
effect of voltage ramping when domains change voltage.
You can see a demo of these
capabilities in this related blog.
With warp speed, you make every test in your regression both
a functional _and_ and low-power test.
Lower power, higher quality.
Isn't that what it's all about?