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I trust that most of you have seen the recent flurry of blog posts and articles about the new Cadence "EDA360" vision. I was working on a blog entry on how this links to my world of verification when I saw my colleague Jack Erikson post "What Does EDA360 Mean for Logic Designers?" Since I liked his title, I've stolen borrowed and adapted it for my own purposes. This is by no means the final word on the impact that EDA360 will have on verification engineers, just some of my initial thoughts that I hope will prompt some responses and discussion.
As Jack notes, this vision is partly based on the observation that our customers are starting to see IP integration as a key component of their SoC projects, on a par with or even more important than IP creation. Additionally, the "IP" being created and integrated is in both hardware and software form, even for companies that were traditionally pure silicon providers. Of course, in the verification world there are clear counterparts to this flow in the creation and integration of verification IP (VIP), some of which already straddles the hardware/software boundary.
These aspects of EDA360 actually intersect the verification engineer's role in multiple ways. Verification teams will do more VIP reuse and integration themselves, while verifying hardware designs with less focus on new IP functionality and more on proper IP integration, while transitioning to SystemC-based design with a mix of different design representations at different times in the project, and while shifting to do more and more hardware-software co-verification.
So what do you think EDA360 means for verification engineers?
The truth is out there...sometimes it's in a blog.