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Although I attend a number of
conferences and tradeshows each year, most of these are rather EDA-centric. But
last week I was in Irvine for the eighth annual International System-on-Chip
(SoC) Conference. It is a fairly small event -- more like a workshop in some
ways -- with a single track over its two days. I do not believe that I have ever
been to any conference with such a diverse range of topics in one track. Just
check out the program;
the topics range from details of silicon structures for new kinds of memories
all the way up to high-level programming requirements for multi-core systems.
My Universal Verification Methodology (UVM) talk fell somewhere in the middle.
The best aspect of such a diverse conference
is that attendees hear talks that they would not otherwise select, and that was
certainly the case for me. The downside is that some potential attendees will
look at the program and decide not to attend because only a subset of the talks
falls in their primary areas of interest. The consensus among a group of us chatting
at lunch was that the conference might benefit from a few parallel tracks, for
example silicon technologies for SoCs, SoC design and verification case
studies, and system-level development techniques. Of course, it's a
chicken-and-egg problem for any conference to both expand its program and grow
its attendance, especially in the current economy.
I generally consider any event I
attend, whether a "management skills" training course or a technical
conference, as a success if I take away a couple of new ideas. By this measure,
I count my attendance at the SoC Conference as worthwhile. Across the broad
agenda, one panel and two talks grabbed my attention and gave me something to
think about. The panel was "Emerging Technologies, Trends, and Possibilities in
Designing Multicore SoC Platforms" and included my Cadence colleague Steve
Leibson. What most struck me was the almost complete lack of alignment among
the panelists on what the big issues are for SoC design and verification.
Perhaps that's not surprising on a panel whose topic was nearly as broad as the
Dr. Jeff Parkhurst of Intel
delivered an interesting talk on SoC solutions in the "More than Moore" environment.
Steve already posted a nice summary
of the main points, but a few of Dr. Parkhurst's statements caught my ear. He
summarized well some of the main challenges for SoC developers, including
software, mixed-signal ("little A/big D"), architecture, micro-architecture,
and low-power verification. He noted quite correctly that verification is never
truly done, so that all we can do is answer "when is system validation good
enough?" Finally, I couldn't help but chuckle when he twice mentioned the "two-year
cadence" of the march to smaller nodes.
Finally, the most thought-provoking
talk for me was by Professor Mel Breuer of the University of Southern
California. He started by pointing out that contemporary deep-submicron chips all
have manufacturing defects, something that was not the case back in the MSI/LSI
days. To avoid 0% yield, SoCs are designed with logic and memory redundancy so
that defective structures can be disabled; speed-related defects can be handled
by "binning" parts for different maximum clock frequency.
Dr. Breuer proposed extending this
approach to also yield (and sell) parts where specific classes of defects
render the chips "good enough" for specific applications. For example, a small
arithmetic error might not matter for a graphics chip where a wrong pixel or
two would never be noticed. He showed some empirical results demonstrating that
0.1-0.2% of the bits in an audio memory could be bad without being detectable
by the human ear. It was an intriguing topic and I went home thinking that
chips might not always have to be perfect, recalling a famous example in which
only a small percentage of defective CPUs were ever exchanged by the end users.
One final comment -- I was surprised
by how few of the attendees I saw using laptops, tablets or smart phones over
the course of the two days. Considering the range of topics and the likelihood
that few of us fully understood every talk, that's quite impressive. I enjoyed
the breadth of the program and exposure to some new technologies, and I
certainly encourage all of you to consider attending the SoC Conference in the
The truth is out there...sometimes
it's in a blog.