Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Although I attend a number of
conferences and tradeshows each year, most of these are rather EDA-centric. But
last week I was in Irvine for the eighth annual International System-on-Chip
(SoC) Conference. It is a fairly small event -- more like a workshop in some
ways -- with a single track over its two days. I do not believe that I have ever
been to any conference with such a diverse range of topics in one track. Just
check out the program;
the topics range from details of silicon structures for new kinds of memories
all the way up to high-level programming requirements for multi-core systems.
My Universal Verification Methodology (UVM) talk fell somewhere in the middle.
The best aspect of such a diverse conference
is that attendees hear talks that they would not otherwise select, and that was
certainly the case for me. The downside is that some potential attendees will
look at the program and decide not to attend because only a subset of the talks
falls in their primary areas of interest. The consensus among a group of us chatting
at lunch was that the conference might benefit from a few parallel tracks, for
example silicon technologies for SoCs, SoC design and verification case
studies, and system-level development techniques. Of course, it's a
chicken-and-egg problem for any conference to both expand its program and grow
its attendance, especially in the current economy.
I generally consider any event I
attend, whether a "management skills" training course or a technical
conference, as a success if I take away a couple of new ideas. By this measure,
I count my attendance at the SoC Conference as worthwhile. Across the broad
agenda, one panel and two talks grabbed my attention and gave me something to
think about. The panel was "Emerging Technologies, Trends, and Possibilities in
Designing Multicore SoC Platforms" and included my Cadence colleague Steve
Leibson. What most struck me was the almost complete lack of alignment among
the panelists on what the big issues are for SoC design and verification.
Perhaps that's not surprising on a panel whose topic was nearly as broad as the
Dr. Jeff Parkhurst of Intel
delivered an interesting talk on SoC solutions in the "More than Moore" environment.
Steve already posted a nice summary
of the main points, but a few of Dr. Parkhurst's statements caught my ear. He
summarized well some of the main challenges for SoC developers, including
software, mixed-signal ("little A/big D"), architecture, micro-architecture,
and low-power verification. He noted quite correctly that verification is never
truly done, so that all we can do is answer "when is system validation good
enough?" Finally, I couldn't help but chuckle when he twice mentioned the "two-year
cadence" of the march to smaller nodes.
Finally, the most thought-provoking
talk for me was by Professor Mel Breuer of the University of Southern
California. He started by pointing out that contemporary deep-submicron chips all
have manufacturing defects, something that was not the case back in the MSI/LSI
days. To avoid 0% yield, SoCs are designed with logic and memory redundancy so
that defective structures can be disabled; speed-related defects can be handled
by "binning" parts for different maximum clock frequency.
Dr. Breuer proposed extending this
approach to also yield (and sell) parts where specific classes of defects
render the chips "good enough" for specific applications. For example, a small
arithmetic error might not matter for a graphics chip where a wrong pixel or
two would never be noticed. He showed some empirical results demonstrating that
0.1-0.2% of the bits in an audio memory could be bad without being detectable
by the human ear. It was an intriguing topic and I went home thinking that
chips might not always have to be perfect, recalling a famous example in which
only a small percentage of defective CPUs were ever exchanged by the end users.
One final comment -- I was surprised
by how few of the attendees I saw using laptops, tablets or smart phones over
the course of the two days. Considering the range of topics and the likelihood
that few of us fully understood every talk, that's quite impressive. I enjoyed
the breadth of the program and exposure to some new technologies, and I
certainly encourage all of you to consider attending the SoC Conference in the
The truth is out there...sometimes
it's in a blog.