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Facing a verification overrun, you poached resources, clocked overtime, and kept the slip to a few weeks. Momentarily proud of your diving catch, your GM just told you to get out on the road to sell an additional 400,000 units or your program will be canceled. As you examine every customer looking for the elasticity that will keep you profitable, you plan to find a new approach to Silicon Realization.
This is the reality facing business owners as they plan their verification projects. At the 90nm node, International Business Strategies, Inc.(IBS) reports that the verification cost is approximately $6.2M. At 22nm that cost will rise to $36M. With ASPs remaining relatively constant through this period, the number of chips a company must sell for a program to be profitable rises linearly. In another study, Databeans, Inc. forecasts the average selling price
(ASP) for all logic devices to be approximately $1.67 in volume for the
next few years. These ASPs indicate that a simple verification cost overrun of 10% translates into the need to sell 400,000 more units at 90nm and 2,200,000 more at 22nm.
Quantitative and Qualitative Elasticity
The numbers above are certainly averages, but provide a reasonable sense of scale for the issue. Digitimes reported that Apple sold 47 million iPhones in 2010 and Ericsson reported that it sold 1 million base stations between 2007 and 2010. While both are wireless products, they have very different markets, customers, and unit costs. In each company, business owners determine the features needed to serve their customers, the size of their serviceable markets, and the effective unit price at which those products will become profitable. Those business owners can model the risk mitigation for an overrun such as the one described in the beginning of this email with a linear projection of additional sales, but the more qualitative measure is the impact of missing a market window or arriving at a point of lower unit prices which can further impact profitability. Either way, there is a limit to the elasticity of a given business.
Reining In Your Middle Line to Protect Your Bottom Line
Given the boundaries of an available market, the variable in your hands is the verification project cost. You already know that verification is a specialized task requiring specific sets of niche skills. Those niches, including higher levels of abstraction with transaction level modeling, low-power verification, algorithmic verification, gate-level simulation, and more have evolved their own teams within your organization, sometimes even with their own localized methodologies. While this approach serves to solve complex problems well, it lacks the cohesion necessary to give the program a clear sense of the progress toward verification convergence.
The Cadence Silicon Realization solution for verification offers a new, holistic end-to-end approach approach to verification. It recognizes the value of the specialized niches you need, but seeks to remove the inefficiencies that arise when you lose sight of the overall project. It offers new technology and methodology to fuse these niches together through an automated plan that carries the verification intent for your project. With that plan you will be able to improve your overall productivity by assigning portions of the plan to each niche and continuously monitoring the overall program's progress toward verification convergence. Doing so provides an unprecedented ability to manage the verification costs, which are 60% of your middle line, thereby protecting your bottom line.
The first step to managing verification risk is education. You can start with the Metric Driven Verification white paper as well as your local Cadence account team. Feel free to contact myself or John Brennan as well.
Adam Sherer, Cadence Product Management Director