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I hope you have all seen by now, Accellera has announced
the official production release of the Universal Verification Methodology (UVM)
1.0 standard. My colleagues Richard
Krolikoski and Adam
Sherer have already blogged about the release and its contents so I'll
refer you to their posts rather than cover the same ground here. What I really
want to do is to congratulate the Accellera VIP Technical Subcommittee (VIP-TSC)
for accomplishing something that some in the industry doubted could ever
an occasional gadfly on the VIP-TSC's progress, there have been times when I
have been doubtful myself whether our dream of a true verification methodology
standard would come true in a timeframe short enough to matter. In my last blog
on the matter back in September, I dared to suggest that the VIP-TSC consider
dropping a feature or two to get UVM 1.0 out before the end of 2010. I
identified the register package as having the greatest risk, from which some
concluded that Cadence didn't want a register package in the UVM. Of course we
did; our customers were clear that it was higher priority than some of the
other possible additions.
happened was that Accellera dropped none of the proposed major new features for
UVM 1.0, although they did wisely trim off some details, and ended up releasing
three months later than their original target. Yeah, I predicted that when
I sized up the UVM status back on September, but I've kept silent until now
because it was clear that the VIP-TSC was making good progress and that all parties
remained strongly committed to the new standard. But this is not an "I told you
so" blog post; in fact it's just the opposite.
mix metaphors rather badly, this gadfly is eating a little crow right now. I was really worried that trying to fit the register package, simulation phasing, TLM
2.0 support, and a few other new features into UVM 1.0 was too ambitious,
risking a delay well into 2011 or even a complete failure to converge on a
standard. But Accellera pulled it off! For the register package in particular,
for which all three major simulation vendors originally had their own approach,
the VIP-TSC seems to have arrived at a standardized solution that everyone can
the grand scheme of things, a few months of slip (especially with two weeks of
widely celebrated holidays in the middle) don't matter much. The industry now
has achieved a true milestone for verification and for EDA standards. I give
all the credit in the world to the VIP-TSC members who slogged through the
trenches to arrive at the UVM 1.0 standard and to the leaders who kept their
eye on the end goal despite all the obstacles along the way. This is the
beginning of a whole new era and I couldn't be happier. Gadfly out.
The truth is out there...sometimes
it's in a blog.