A Classification of ESL - High Level Synthesis Tools

These days, there is a lot of talk of what the next design methodology for Digital Systems will be and how this methodology will be the replacement of RTL Synthesis. The term ESL (Electronic System Level) is used as a general term for the new wave of modeling and synthesis for digital systems.

We have noticed that the term ESL is a very different concept for different people. It might mean a modeling approach, a design approach or a combination of both. In this blog we are not attempting to define what ESL is, but we are trying to provide a brief classification of the different types of ESL / High Level Synthesis tools.

Before, we attempt to classify the different types of ESL / High Level Synthesis tools, let us, for the purpose of this blog, define an ESL / High Level Synthesis tool as follows:

“An ESL / High Level Synthesis Tool is a software tool that takes a high level description of a digital system and transforms this description into an RTL (Register Transfer Language) description in a language such as VHDL or Verilog.”

Additionally

“The RTL description synthesized by the ESL / High Level Synthesis tool must be synthesizable into a gate level netlist by an RTL Synthesis tool such as Cadence’s RC”.

Currently, there are three kinds of ESL Synthesis tools being marketed as follows:

The first kind are tools which take a graphical / data-flow description of the system and usually translate this description into “structural RTL” (a netlist of synthesizable block instances) which have been originally written in a parameterizable way.

The second kind are tools which take a single threaded computer programming language (usually C or C++ without support for threads) and translate this description into either a single synthesizable RTL block or into a structural pipeline of RTL blocks.

The thrid kind are tools which take a multi-threaded computer programming language (usually SystemC) and translate this description into a “structural RTL” description which can be an arbitrary netlist of synchronous state machines.

Cadence’s C-to-Silicon Compiler is an example of the third kind of ESL / High Level Synthesis tools. As said before, the basic characteristic of this kind of tools is support of multiple threads in a similar fashion that support for multiple processes (threads) is an inherent characteristic of RTL based synthesis tools and Hardware Description Languages.

Supporting multiple threads brings the following advantages:

• Support of multiple clock environment in a similar way that RTL synthesis tools support multiple clocks.
• Support of multiple concurrently executing blocks in a similar way that RTL synthesis tools support multiple processes (always blocks in Verilog or Process block in VHDL).
• Support of multiple instances in a similar way that RTL synthesis tools support “structural” code.
• Support of reactive blocks. This is usually not possible single threaded approaches.
• Support of feedback loops. This is usually not possible, or difficult to implement in single threaded approaches.
• Support of control structures. This is not usually possible in single threaded approaches or in graphics based approaches.
• Support of non-sample based interfaces. Burst transfers and other type of interfaces usually require the implementation of reactive blocks such as DMAs. This is not possible in single threaded environments.
• Support of Mealy style state machines. Mealy type state machines usually require two threads (one for the combinational logic and one for the registers), therefore they cannot be implemented in a single threaded environment.
• Support of non-blocking constructs. All statements in a single threaded environment are blocking.

These advantages are what makes the third kind of ESL / High Level Synthesis tools the only viable alternative to RTL synthesis. Single threaded environments or graphics based data flow entry tools cannot, and probably never will, be able to describe a complete digital system as it is currently done with RTL based tools

This Team ESL posting is provided by Dr. Sergio Ramirez, Core Comp Architect for the C-to-Silicon Compiler high level synthesis product.