Achieve 80% Less Late-Stage RTL Changes and Early RTL Bug Detection

15 Aug 2022 • 5 minute read

Leveraging Jasper RTL Design Signoff App for Early RTL Bug Detection and Avoiding Late-Stage Changes in RTL

The number of asynchronous clock domains in chip designs continues to increase, driven by dynamic power optimization. Together with multiple reset domains, the multitude of clock domains has increased design complexity. It has become challenging to ensure that the designs are complete, correct, and adhere to necessary coding rules before handing them off for RTL verification and implementation. It is challenging to verify that the desired chip can be implemented from the RTL without any respins.

Traditional static verification techniques such as Lint, DFT, and structural CDC/RDC checkers cannot provide this assurance, and designers using static techniques alone face challenges like noise and missed violations. Structural Lint technology needs to be significantly augmented with formal assisted technology to enable designers to catch more issues that are genuine.

RTL Designer Signoff Solution from Cadence helps the user identify RTL bugs at a very early development stage, saving a lot of effort and cost for the design and verification team. Our reputed customers have confirmed that using RTL signoff for their design IP helped save up to 4 weeks and reduce the late-stage RTL changes by up to 80%.

The efficient schemes like the one-stop knowledge resource for Clock Domain Crossing (CDC) verification App and the One-stop knowledge resource for Superlint (SL) App are available in rapid adoption kits (RAKs). The RAKs can be used to quickly learn about recent technologies and resolve issues. The best practices are captured in RAKs and serve as ready solutions for customers. There are methodology articles with advanced solutions at the Cadence Support portal site; it has collated years of experience of experts to provide tips and techniques to help meet your design PPA and TAT requirements. The resource is available 24X7.

Read more to learn how Jasper RTL Signoff boosts the designer's confidence in RTL before verification and implementation.

Jasper RTL Signoff App

Jasper RTL Signoff brings the power of the leading Jasper gold functional verification platform to the RTL developer's desktop.

The RTL signoff process is automated to ensure the RTL meets the design rules before verification and implementation. For this automated RTL signoff process, the benefits are

Robust IP blocks to ensure reusability
High quality and CDC clean RTL
Resolution of RTL Issues at the earliest stage
No RTL change during implementation.

Why You Should Use Jasper RTL Signoff App

There are many problems with the existing structural-only RTL signoff schemes like

Incomplete static rule-based checks
Manual debugging without good root-cause analysis
No functional checks for confirming which violations can be waived
Too many checks at a later stage in the flow

The bugs can be deducted earlier by conducting these checks at some earlier stage in the design flow. Using Cadence RTL signoff solutions, designers can check all issues early in their RTL IP design. This solution involves two apps, Superlint and clock domain crossing (CDC). The Superlint App has combined the traditional RTL linting and formal verification capabilities, deriving the most complete set of functional checks from the RTL automatically. Similarly, the CDC App offers a metastability injection flow for rigorous CDC verification for a more comprehensive signoff.

Features

Jasper RTL Signoff app supports metastability-aware verification in both formal verification and simulation
It has the injection capability in clock and reset crossings
It also provides a good debug environment to detect metastability-related issues
It can perform functional checks without any testbench requirements

Jasper Superlint App

Linting is a set of basic checks that check the correctness of the RTL code.

It checks:

Basic standards and naming conventions
Constructs in the code for any mismatch between simulation and synthesis
Sufficient controllability and observability to meet DFT goals

Using this app, we can also derive automatic property checks from the RTL for:

Arithmetic overflow/ range overflow
Livelock/deadlock checks for finite state machines
Reachability checks

All these go beyond the traditional tools available in linting and give you a much more thorough examination.

Many of our customers have used this to check their designs for RTL signoff improvement and reducing time to market, as they can find the bugs earlier and are critical to this if they lessen the late-stage RTL changes.

Jasper CDC App

SoCs have become complex due to added functionality and multiple asynchronous clock domains, where signals frequently travel from one clock domain to another. In hardware, all such Clock Domain Crossing (CDC) movements can cause fundamental issues due to signals with different frequencies in our design, such as:

Metastability propagation
Data Loss/Corruption and
Data Coherency issues due to re-convergence

Traditional methods like RTL simulation or static timing analysis alone are insufficient to verify the consistency and reliability of the data transferred across clock domains.

Many CDC-related bugs are detected only post-silicon verification necessitating costly re-spins while using the traditional tools. Such techniques are expensive; these days, designers intend to recognize and mitigate such issues earlier in the design process. Jasper CDC helps to provide clean RTL in less time than traditional tools. It is the only CDC solution with industry-leading formal technology for functional checks and violation/waiver handling.

Further, we can reduce violations, noise by using formal debug technologies; apart from this, the auto waiver feature is unique.

CDC App Flow

Summary

The best-in-class Formal RTL Designer Signoff Solution uses Superlint and CDC Apps. It offers:

Superior functional Checks and handling violations
Full set of checks necessary for RTL design signoff
World-class formal technology now brought to RTL designer's desktop
Excellent integration with Xcelium logic simulator

The Jasper technology supports the designers in identifying the actual problem violations, confirming fixes, and providing justification for waiving the violations that are not problematic. Additional automatic formal checks are provided for functional verification of many design aspects, using properties derived automatically from the RTL. This app allows RTL designers to sign off higher quality, more robust, and CDC/RDC-clean designs months earlier in the project schedule. Our reputed customers have confirmed using RTL Signoff for their design IP, which helped save up to 4 weeks and reduce the late-stage changes in RTL by up to 80%.

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