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Debugging low-power designs is its own unique challenge in the verification field. Between confirming varying requirements across different power domains and the challenges associated with assuring correctly retained chip states through power cycles, specific low-power verification methodologies are required to reach tapeout. Luckily, Verisium Debug has everything you need to make your low-power debugging as simple and painless as possible.
If you’re familiar with vManager, you’ll love using Verisium Debug—it’s Cadence’s next-generation debug solution, and it works natively with Xcelium just like vManager. Utilizing AI to automate the manual processes involved with debug, Verisium Debug can speed up your debug time by up to 3x—and given that debug frequently represents half of the total time an engineer spends manually working on a design, this is a huge improvement in the overall efficiency of verification.
Here, we’ll go over how to get started using Verisium Debug and discuss a few quick tips on how to use the software.
First, install it and set up the environment: use %/ setenv VERISIUM_DEBUG_ROOT <path to installation directory> and %> xrun-64 -debug_opts verisium_pp +access+r <HDL files> \ -lps_1801 <UPF files> -lps_common_options-input input_lp.tcl\+vwdb+shm2vwdb=1. This will automatically enable the smart logging features as well, SmartLog. You can then invoke Verisium Debug with an “ida.db” located in your current directory, or you can pass Verisium Debug explicitly to your design (-lwd) and waveform (-db) location.
In Verisium Debug, under the Power Browser tab, you can view your design hierarchy according to the low power intent of each domain. Power domains are grouped by the design object that defines them, and each includes their lists of related scopes, isolation and retention strategies, and supplies. Icons next to the domain name indicate the current state.
Figure 1: The power browser
The Design Browser is power-aware as well—it shows special icons for low-power simulation objects, like instances and liberty cells. The signal list includes power supply sets, shut-off conditions, and supply nets as well.
The Exploration tool can help you see how your RTL code will operate in low-power environments—something not frequently obvious during design. Use this tool to query for RTL signal or supply net connectivity.
Figure 2: The Exploration tool
The SmartLog tool, automatically enabled when Verisium Debug is invoked in the way described previously, contains messages regarding low power. These messages are linked to their relevant sections of the source and contain tags that allow them to be easily filtered.
Verisium Debug also has a huge number of driver tracing support features. Low-power-related causes are integrated into Verisium Debug’s driver tracing results, including power and Liberty shutoff, isolation and retention states, XPROP causes, and more. It also supports these in UPF objects during power shutoff and switch.
This traceability of RTL and UPF objects makes understanding the link between RTL, UPF, and low power causes easy and clear, vastly speeding up your debugging process.
Figure 3: Driver tracing support
Verisium Debug also offers power-aware schematics to assist in the visualization of your low-power verification. Low-power domains are annotated above the RTL schematics, and each one is given a background color to make them easily distinguishable. When a power domain is turned off, it will turn grey. The different instance types have special icons to denote if they are power-aware or non-power-aware.
Isolation rules and ports have some extra features, too—icons next to them indicate the clamp type and their current status. Isolation ports show up as wider than regular ports to make them easier to identify at a glance, and you can easily access the source right from the isolation port for both control signal definition (from RTL) or rule definition (from UPF).
This only scratches the surface of what Verisium Debug can do to make your low power—there’s a lot more beyond this. For more information, check out Verisium Debug’s product page.