Accelerating the Next Big Shift in Verification

Today Cadence announced that we are aligning our proposal to the Accellera Portable Stimulus Working Group (PSWG) with the other two commercial vendors in this market – Mentor Graphics and Breker – to deliver a joint contribution, intended to accelerate the standardization process. More on this below. We at Cadence believe that portable stimulus standardization will be the hallmark of next generation verification automation. Looking at a recent key-note at CDNLive India, Samsung seems to agree on the importance of software driven verification as well!

During my recent trip to India to attend and present at CDNLive in Bangalore, it was great to see the key note of Samsung’s VP Device Solutions, India Labs, Balajee S., emphasizing the importance of software driven and scenario driven verification techniques. In his keynote Balajee mentioned that Samsung is using our Perspec™ System Verifier to “generate test cases that run several billions of cycles each week”. Standardization is crucial for this next big shift in dynamic verification techniques, hence the announcement today.

In his keynote at CDNLive India, Balajee reviewed the transformation of compute needs, showing a graph of devices per users over time. He outlined four distinct eras:

• The 1^st era spanning from the 60s to the 80s with up 10MM+ units of minicomputers was focused on select work tasks
• The 2^nd era of personal computing and desktop internet in the 90s and 2000s reached 1B+ units and offered broad-based computing for specific tasks
• The 3^rd era reached 10B+ devices enabling the mobile internet during the past decade, making computing part of our lives
• The 4^th era is the era to which we are in the midst of transition to – enabling the internet of things.

Balajee described the eco-system participants from data-creators (the devices we carry) to data acquisition services (Hadoop, Cloud) and analytics (openstack™ and the Open Compute Project) and then clearly articulated the challenges for verification. While the fundamentals haven’t changed – it is driven by correctness, completeness and stimuli generation strategies. However, diversity and complexity have increased significantly, new SoC architecture cycle time has shrunk, verification turnaround time has become more aggressive and the number of SoCs per engineer per year has increased significantly.

I especially liked Balajee’s discussion of how the mindset of verification needs to change, from “are we building it right?” to “are  we building the right thing?”, from “Think SoC” to “Think Systems”, from “1^st day success” to “Good stress”, from “Multiple SoCs” to “Platforms and Derivatives” and from “non-overlapping IPs and SoCs” to “reusable IP/Subsystems/SoCs”.

The subsequent slide that he used to outline the methodology change is similar to what I used in previous Blogs, like “The Next Big Shift in Verification” and what I described in “Top Down SoC Verification”. Bottom line, verification needs to be re-usable horizontally and vertically, and across use cases. 

Verification Methodology Change - Courtesy Samsung, Balajee S.
as presented at CDNLive India, August 19th 2015

In summary, Balajee called for the need for simulation less Integration, modes and register map verification, inferring and generating testbenches catering to multiple configurations of SoCs from IP &  SoC Metadata. Watch that space, it is related to automating the assembly of the design and the verification environments, as well as formal verification. He called for hybrid platform with fast models for rapid prototyping and development of driver software, as well as seamless emulation platforms for software stack bring up and validation, citing our Palladium and Protium platforms.

With respect to software driven and scenario driven verification, he called for subsystem and SoC-level stimuli generators that provide standard compliance suites and library for widely used protocols, generate portable stimuli that are language agnostic and can be re-used all the way from pre-silicon to post-silicon environments. They need to allow easy modelling of system architecture, comprehensive inference of data and control paths scenarios as well as the ability to merge scenarios to create longer and deeper tests. This is where Balajee’s mention of Perspec comes in, as they use it for generating test cases that run several billions of cycles each week in their verification.

It is this last area which has enjoyed special focus during the last two years. It all became very public during a DVCON panel in 2014, in which graph based and model based techniques were discussed quite heatedly as written up by Ed Sperling here, here and here. We subsequently announced Perspec System Verifier in December 2014, ST Microelectronics talked about their use of software and scenario driven verification at DVCon 2015 and DAC 2015.

Today’s announcement that Cadence, Mentor Graphics and Breker will provide a collaborative technology contribution to the Accellera PSWG  that is intended to help accelerate development of a standard that meets both vertical and horizontal stimulus and test reuse requirements.

Specifically, the donation will include

• A concise specification language for use-cases that allows high level abstraction of stimulus and tests, including coverage and results checking
• Semantics to allow generation of tests by automation tools in a variety of languages and tool environments with consistent behavior across multiple implementations from simulation through emulation to FPGA and post-silicon
• A model-based approach supporting graph-based descriptions of stimulus and test scenarios as well as a library of predefined utility functions plus support for user-defined functions helpful when generating system-level portable stimulus and tests

This is a big deal for the industry! The three commercial vendors are aligning their contribution to the standards organization. There is a give and take in all the tools to make sure they can support the future standard, and that has already been done. This is actually how Accellera encourages contributions. The guidance that they offer in the Accellera Policies and Procedures, state that “… Accellera prefers not to have competing contributions. It is recommended that complementary contributions are worked out among different Contributors…”.

So with the three companies planning on contributions, it made good sense for all of us to collaborate and work toward a single contribution.  Based on Cadence’s experience in the past working with Mentor Graphics to collaborate on developing OVM and contributing this to Accellera which lead to the standardization of UVM, we are confident in this approach.

So what about competition? This is all meant to enable interoperability. We strongly believe that portable stimulus will be the hallmark of next generation verification automation and be as important to verification as HVLs and Metric Driven Verification, so it will ultimately be a large market with lots of room to differentiate. Having a standard that protects investments companies make in developing portable stimulus only accelerates the growth of the market.

You can find out more about the contribution here. We continue to live in fascinating times!

Frank Schirrmeister