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With the increasing complexity of system-on-chip (SoC), the associated software stack is now integral to the system’s functionality. The software stack impacts the development cost and schedules for both the SoC provider and their customer. Software is a necessity today to sell silicon and manage the development schedule. Any delay in the software schedule delays the time to revenue. The impact of delayed software testing until the first silicon arrives back from the fab are enormous. It is essential to handle this rapidly increasing system design complexity and time-to-market pressures through pre-silicon hardware debugging, software validation, and co-verification while preserving functional congruency between emulation and prototyping.
Analog Devices (ADI) bridges the physical and digital world by transforming complex real-world signals into insights and actions, profoundly improving lives. This requires solutions that combine analog hardware, digital hardware, and software. ADI’s goal is to have “zero defects” in their shipped products.
ADI has been using emulation platforms primarily focusing on digital and system-level use case scenarios. Their primary goal was to organize and coordinate the tasks of the firmware and hardware design verification (DV) team, ensuring that the firmware and application programming interface (API) boot was successful on day one. They also wanted to find an acceleratable platform for system use case scenarios that trade-off accuracy and performance between simulation and SystemC models.
The ADI SystemC verification team performs early firmware validation using the SystemC models. They want to see the actual register transfer level (RTL) in place, co-verified with the actual firmware before the silicon arrives from the fab. Increasing design and firmware complexity makes verifying the enormous amount of firmware, device drivers, and complex use cases challenging. Software-driven hardware co-verification and providing complete system solutions early to customers become vital for design wins. Also, testing firmware and system use case scenarios using a simulator is not practical and time-consuming.
Design and firmware complexity challenges:
ADI also faced debugging challenges in emulation, such as continuous wave dump to create a waveform database using Cadence Simulation History Manager (SHM) for long-running scenarios, especially to debug during a bring-up, generating overhead for run time, and time-consuming efforts to dump significant traces.
ADI design architecture consisted of a complex digital top with a multi-processor design, interconnects, peripherals, and digital intellectual properties (IPs). These formed the major crux of the design, validated through three different boot models, DDR4, eMMC 5.1, and QSPI. The second part of the architecture is the UART. The DV team used it primarily to register read/write operations and have driving scenarios with different interrupts and baud rates. It did not have the debug messages printed physically when needed by formal validation teams, and the terminal formed an essential requirement for them. Also, ADI had a complex ethernet JMI interface with an ethernet media access controller (MAC), PHY, universal verification methodology (UVM) Turbo Boost (TB) component, and VIP for verifying protocol functionality. They also wanted to enable a host-based boot mechanism using Ethernet. For firmware, ADI wants the JTAG-based debugging and validate the device and custom peripheral drivers as soon as possible.
The Cadence memory models were purely meant for simulation and not emulation. As such, they needed to replace simulation memory models with emulation-friendly ones designed to run at high performance in the emulator. In addition, Linux boot would take many days with simulation, and the format team wanted the messages to be printed in the terminal.
The verification of complex Ethernet traffic and use cases requires long tests that are impractical for simulation. And for the Ethernet solutions to verify the design complexity, traffic, and use case scenarios, these issues will be long-running in the simulation. ADI wanted them to accelerate Verification IP (VIP) and the overall solution. A long-running test takes about 14 hours to complete in simulation, delaying the overall hardware and software co-verification and making the general verification too slow. ADI teams wanted a solution to address this.
ADI addressed the design, firmware, and debugging challenges using Cadence Dynamic Duo - Palladium® Z2 emulation and Protium TM X2 FPGA-based prototyping platforms.
Palladium Z2 is most widely used for easy hardware validation and debugging. Protium X2 primarily accelerates hardware and software co-verification for speed and development. ADI used Palladium for functional verification, supporting a UVM testbench environment, full vision, and faster debugging.
Protium X2 supports faster bring-up time than traditional FPGA prototyping. Protium X2 provides high debug visibility through Software Vision and system-wide, at-speed probing using external data capture cards (DCC). It features a congruent compile flow with Palladium, in-circuit emulation (ICE), and virtual and hybrid emulation modes.
As a solution, ADI utilized the virtual UART on the Dynamic Duo, integrated their SoC design with the memory model portfolio from Cadence, and assessed the boot scenarios effectively. This was possible because of the congruency flow established between Palladium and Protium. The same compiler has been used for Palladium and Protium. No RTL modification is required when you migrate to Protium. ADI could reuse most of the scripts from Palladium to Protium, which immensely helped them accelerate the overall bring-up time.
For complex functional debugs, the ADI team shifted back to Palladium with less compile time to debug and returned to Protium to use it as a regression platform. This is the most flexible congruency flow that other traditional platforms do not have today.
Simulation-compatible memory models: These models are not supported on Cadence Dynamic Duo, and the Linux boot takes days with simulation.
Solution: ADI replaced the simulation memory models with the Cadence Palladium Memory Model portfolio, which provides easy integration for acceleration. The pre-validated plug-and-play models helped ADI to accelerate the Linux boot validation.
UART simulation setup: No support to send/receive data from the terminal for FW validation. It does not print FW debug messages in the terminal.Solution: ADI replaced the RTL UART with a Virtual UART, which supports sending and receiving data from the terminal for firmware validation and supports all the standard and non-standard baud rates.
Ethernet VIP Simulation setup: Simulation-based Ethernet VIP is not supported on the emulation platform, and accelerable VIP (AVIP) is required to accelerate Ethernet tests.
Solution: For Ethernet solutions, ADI started using AVIP, which supports simulation and emulation platforms. With the AVIP, ADI also had a synthesizable Verilog driver to drive traffic through the DPI-C to interact with the Ethernet TB component with chip package protocol (CPP) proxy through ethernet bus functional model (BFM) to ethernet device under test (DUT).
Connect directly with applications for live Ethernet testing
Solution: Apart from these solutions, ADI wanted to verify the customer use case scenario where real-time applications and hosts sit externally and drive the live ethernet traffic. For the Joint Test Action Group (JTAG), ADI has the IO board connected to the CPU with the help of the JTAG debug variable to debug.
ADI achieved a reduction in run time to 5 minutes from 14 hours, reduced firmware boot speed to a few hours from days, and enabled JTAG debugging on the IO board.
While the Palladium performance, clocking the design at 748 kHz, was nearly 170X faster than the simulation, it was insufficient for the firmware team’s requirements, high domain utilization restricts the setup that multiple FW engineers will use, and ethernet AVIP does not support MACSEC and PTP.
To address the need for more speed, ADI evaluated traditional FPGA but found several drawbacks and approached Cadence for a solution. Cadence Protium X2 addressed the deficiencies faced by the ADI teams. Traditional Field Programmable Gate Arrays (FPGAs) have multiple clock limitations, and Application Specific Integrated Circuit (ASIC) memories need tweaking. ADI could overcome the limitations using Protium X2 with its unlimited design clocks and automatic memory compilation. FPGA partition remains a significant task; traditional FPGA has been purely manual, whereas Protium is automated.
Time closure has been a nightmare in traditional FPGAs, especially for high-complexity designs. In comparison, Protium offered no hold violations and improved closure.
In-circuit bring-up, in traditional FPGA, the FPGA P&R iterations are long; Protium provides automatic constraint generation, which has dramatically helped ADI and guaranteed P&R success.
ADI vouches that in comparison to traditional FPGA, Protium X2 improves bring-up time, which helped accelerate the overall solution. The ADI team summarizes that Dynamic Duo helped them enable faster firmware boot and system use case validation.
Ease of migration from Palladium to Protium using congruency flow helped ADI reduce overall time. Also, the ADI team received tremendous support from and collaboration with Cadence application engineers and R&D teams.
The Analog Devices team observed:
When designs are getting bigger, embedded software is growing, and project schedules are shrinking, you need an emulation and prototyping solution that provides comprehensive IP/SoC design verification, system validation, hardware and software regressions, and early software development. The Palladium and Protium Dynamic Duo provides control, visibility, and data-center class prototyping, MHz performance for billion gate size designs in a unified compile and debug environment for fast bring-up and complete hardware/software debugging. Contact us if you want to experience this real innovation and groundbreaking technology.