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Welcome to a special multi-part edition of the App Note Spotlight, where we’ll be highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines for SystemVerliog. This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium Parallel Simulator—in fact, they’ll help you no matter what simulator you’re using.
Here in Part I, we’ll talk about some general software practices, and then we’ll follow that up with a quick discussion on SystemVerilog semantics, and some notes on efficient arrays.
General Software Practices
Since SystemVerilog is an object-oriented programming language, your good software practices from other OOP languages should carry over. Here’s a handful of ways you might be able to streamline your SystemVerilog—and other object-oriented programming language—code:
1) Reduce Function or Task Calls
Obviously, optimizing individual functions is a big deal, but an even bigger deal is to simply not call resource-intense functions more often than you absolutely must. Make sure your operations scale well; if your algorithms scale non-linearly (or even linearly when datasets are large), they’ll drag your performance down significantly no matter what you do.
This is the idea that Boolean expressions can be simplified, and sometimes don’t need to be fully evaluated to reach their conclusion. For example, if the left operand of an OR operator is 1, then it doesn’t matter what’s on the right—it’s going to resolve TRUE no matter what. Try to order your Boolean operations so the ones most likely to short-circuit happen first. The compiler will short-circuit complex expressions, so take advantage of it.
3) Remove Loop Invariants From A Loop
If you’ve got assignments inside a loop that won’t change after each iteration of that loop, put them somewhere else. The compiler will try to do this for you, but blocking statements or idiosyncratic semantics may prevent it from doing so. Doing the same assignment over and over wastes simulation time, and your simulator has things to do and places to be, so that’s not cool.
4) Move Expressions and Assignments Inside Conditionals
Whenever a function has conditional branches in it, by definition, each call will only take one of those branches. Because of that, if an assigned or calculated value is only used in one of those conditionals, it’s a waste to calculate or assign that value before the conditional statement. Generally, the compiler will try to do this for you, but sometimes it will be unable to, so it’s easier to simply write your code to ensure it happens every time.
That’s all we have for today—check back next time for some helpful tips regarding SystemVerilog semantics!