App Note Spotlight: Streamline Your SystemVerilog Code, Part II - SystemVerilog Semantics

Welcome back to a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines for SystemVerilog. This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium Parallel Simulator—in fact, they’ll help you no matter what simulator you’re using.

In this section, we’ll talk semantics—but these aren’t throwaway details, they’re SystemVerilog semantics. These are some small things that can show up here and there that can speed up your code without a whole lot of extra effort.

1)      Be Explicit with the Storage of Logic Types

SystemVerilog has a special data type called the logic data type. When a logic type is being used as a wire, you want to be explicit about it, otherwise SystemVerilog says you will get a variable. You don’t technically have to explicitly declare whether you’re using wire storage or variable storage, as the storage can be determined by context, but it’s much faster to choose one at the declaration. The biggest slowdowns caused by implicitly-declared logic types occur when a logic type is being used as a wire, without actually being declared as such. There’s a pretty simple solution here: make sure you declare it as a wire!

As a special note: when you’re profiling your design, (that’s with -profile, or -xmprof if you’re using Xcelium), places where this issue occurs will be flagged as Anonymous Continuous Assignments (ACAs).

2)      Avoid Bit-Blasting Vectors

Here’s another simple one: make sure your operations use the full vector instead of just operating on individual bits whenever possible. While SystemVerilog has constructs, such as generates, which make it easy to operate on individual bits of a vector, it’s often times just as easy to simply run your operations on the full vector instead, and it’s faster, too. The compiler generally won’t give you trouble if your use case is simple.

3)      Minimize String Formatting

SystemVerilog does provide string objects, but formatting these strings is a very expensive operation. String objects have a lot of useful features for writing messages in your verification environment—so using them occasionally isn’t the end of the world—but keep them to a minimum.

As an example: make sure your code only does whatever formatting is required in the event that the string object is actually used. And, when you are running regressions, where farm throughput is critical, make sure you are not wasting time formatting messages instead of doing real work.

4)      Pass Array Objects by Reference

SystemVerilog doesn’t specifically have “pointers” as they’re understood in other languages. That means you can’t create a reference to an object through syntax, but you can specify a function or a task argument as a reference. When the object is simple and small, like an integer or a class handle, it’s faster to pass it by value, but for larger objects, passing by reference is the less expensive operation.

That’s all we have for today—check back soon for a couple more helpful tips!