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2023 is here, and technology trends around Compute Express Link (CXL) and the next generation of AMBA protocols (CHI-E/F) are getting more traction. The biggest challenge of today is the complexity of handling enormous data flow owning to AI, ML, and deep learning applications. To keep up with the pace, new generation interfaces introduce specialized semantics catering to memory disaggregation, cache consistency, techniques to optimize hardware utilization and efficient transaction flows. Verification challenges for system integrators and verification engineers augmented significantly with the advent of these complex interfaces.
Cadence, a leader in the verification space, pilots much-needed system-level solutions to ease bring-up, testing and debug effort and minimize verification cycles for system integrators. This solution is called ‘System Verification IP,’ which includes System Traffic Libraries, System Testbench Generator, System Verification Scoreboard, and System Performance Analyzer. In this blog, we will talk about the system verification scoreboard (SVD) and system performance analyzer (SPA) taking a real life example of workload submission from CHI interface to CXL nodes through ARM CMN700 interconnect.
Data Coherency Testing
Cadence’s SVD is a protocol agnostic scoreboard which works in conjunction with Simulation Verification IPs or Accelerated VIP. The scoreboard tracks information related to transaction flowing through various nodes of interconnect and justifies SoC behavior. Highly sophisticated algorithms working in background fires violations for mis-routed transactions, data integrity mismatches, cache inconsistencies and snoop filter operations.
Let’s take an example of CHI read transaction initiated from one CHI Host node destined to CXL Type3 device. SVD captures this request on CHI Hnf from CHI VIP monitor connected to SVD port and anticipates if response should be returned by CXL endpoint or from the system cache. If transaction is supposed to reach CXL endpoint through CCG port, then SVD checks for data returned by CXL Type3 device and cross-validates the same data fields are translated correctly from CXL to CHI node. Sounds complex? Well, now imagine thousands of those transactions flying in parallel across the SoC. Similarly, you can have multiple input and output ports of SVD connecting various protocol interfaces (DDR, Ethernet etc’). SVD puts together all the right pieces and has been a powerful data coherency checker and debug aid at system level for industry leading interconnect-based designs such as ARM CMNs for simulation and emulation platforms.
Another aspect which is evidently becoming more crucial is system performance. What if we tell you, Cadence’s System Performance Analyzer can showcase latency and bandwidth numbers in a graphical manner automatically? Yes you read it right, SPA does support analysis for various protocol interfaces which can enabled in background when test is being executed. These graphs are created out of the box, enabling drill-down to the transaction level and can be used to debug any performance dips seen at simulation or emulation runs. Below are indicative graphs for SPA connected across CXL, CHI interfaces. User can easily analyze the peak bandwidth utilization, performance bottlenecks and outstanding transaction at any given time during run using SPA generated graphs.
For more information, do visit our System VIP product page.