Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator – Part 1

In a landscape characterized by increasingly intricate designs and rapidly diminishing time-to-market, today’s advanced verticals necessitate innovative strategies that yield exceptional performance enhancements, enabling them to maintain a competitive edge. When creating a verification strategy, focusing on return on investment (ROI) is crucial. By converting financial aspects into technical outcomes, like the number of bugs found per dollar per day, design and verification engineers can prioritize effectively. Verification throughput is the key to achieving this, enhancing speed and reducing turnaround time.

In today's complex design scenario, simulator performance ensures efficient verification throughput. This is especially significant in high-technology industries such as 5G, automotive, consumer electronics, healthcare, and hyperscale computing, where disruptive design innovations are essential to staying ahead of the competition. With shorter time-to-market and project schedules under intense pressure, a high-performance simulator becomes an essential tool. It can significantly minimize verification turnaround time.

Cadence Xcelium Logic Simulator is positioned as a frontrunner in terms of performance, throughput, and overall verification time. The Xcelium simulator has a long-standing presence, delivering exceptional verification quality and leading in simulation performance, regression throughput, and verification turnaround time. Our focus on core simulator performance drives continuous innovation, optimizing performance for RTL, gate-level simulations, SystemVerilog/UVM test benches, and low-power verification. Our portfolio includes powerful core technologies and applications designed to maximize regression throughput.

At Cadence, we seek out-of-the-box performance gains and by implementing best practices,we have successfully delivered performance boosts ranging from 1.2X to 1.5X and in some cases, even exceeding 3X.

Are you curious about how to attain exceptional verification performance? Keep reading to discover key best practices for the Xcelium Logic Simulator that enable the highest level of simulator performance while meeting strict verification deadlines.

Performance Optimization Checklist

Our Cadence Xcelium Logic Simulator expert team has worked together to create a performance optimization checklist to help you achieve exceptional performance gains of up to 3X.

Parameters to Measure

How do we access our performance? Typically, we start with an analysis of our build/compile time and memory utilization, followed by simulation time and memory utilization.

Performance Switches

Our internal teams rigorously strive to optimize the performance of the Xcelium Simulator, focusing on identifying opportunities for improvement across various code constructs, structures, styles, and optimizations. We have introduced a pair of umbrella switches to facilitate this, providing a straightforward mechanism to enable the latest and most advanced performance enhancements.

• -newperf
• -plusperf

Performance Switch: -newperf

xrun/xmvlog/xmelab -newperf <other arguments>

• SVTB/RTL/LPX/GLS optimizations
• Compiler Optimizations

If you want to optimize your simulation scripts, consider incorporating the "-newperf" switch into your xrun/xmvlog or xmelab commands. You can access the latest performance enhancements, such as improvements in SVTB, RTL, low power, GLS, and compiler optimizations. This switch is straightforward to use and will enable you to take full advantage of these optimizations effortlessly.

Performance Switch: -plusperf

xrun/xmvlog/xmelab -plusperf <other arguments>

• Assertions/RTL optimizations

You can also use the "-plusperf" umbrella switch with xrun/xmvlog or xmelab. This switch allows for optimizations related to assertions and RTL. The switches, "-plusperf" and "-newperf," differ in engine behavior. "-plusperf" may exhibit slight variations in engine behavior, but "-newperf" enhances performance without affecting the engine behavior. Both switches undergo rigorous internal qualification and quality checks before being integrated into the system. Some of these optimizations become the default over time, ensuring optimal performance regardless of the switch chosen. We regularly introduce new optimizations integrated into our "-newperf" and "-plusperf" switches. Using these switches in your scripts or simulation methods can boost performance 1.5X to 3X. It is recommended to use the latest Xcelium release with these switches to get the biggest boost in performance.

Profiling

Once the switches have been enabled, profiling and lead to additional performance gains. Xcelium’s profiling can assist in identifying and resolving performance bottlenecks. Using design profiling, you can analyze the top contributors that account for over 5% of your overall performance, allowing you to target and address these issues. Profiling provides various statistics and information on different switches, allowing for detailed insights into the design and optimization. This approach allows for the enhancement of your system and achieving superior performance.

• Analyze top contributors and all >5% of contributors
• Identify performance optimizations
• Review coding styles

Consolidating Performance Data for Run-Time Performance Analysis

Let's explore the process of profiling. Initially, let's investigate alternatives for compiling and displaying performance data. These alternatives consist of simple switches for basic profiling and more intricate switches that provide detailed and comprehensive profiling information.

-status, -status3

You can use the "-status" or "-status3" switch on functions like xrun and xmvlog to gain valuable memory and CPU usage insights. This switch provides details such as CPU time, wall clock time, and CPU utilization. Paying attention to CPU utilization is essential since a low value could indicate problems with LSF or file IO, requiring further investigation. Optimizing CPU utilization is vital to achieving optimal performance.

 -perfstat

Using the switch perfstat offers extensive statistics for each stage of your process, including compilation, lab, and simulation. The switch provides information such as your hostname, the command line options, and the time consumed during various activities like code generation, elaboration, simulation, license acquisition, and snapshot loading. All these critical statistics are saved to the file xmperfstate.out.

-profile

The elaborated profile is an excellent tool that offers a performance analysis report for both the design and test bench without any performance overhead. It reduces the time consumed in different areas, such as test bench versus design, or across various code streams. It allows you to identify bottlenecks and problematic code causing long wait times. With this information, you can take measures to improve performance. The profile also generates an output file named xmprof.out.

xprof

xprof usage adds 10 to 20% overhead while providing additional key insights. It is an advanced instance-based profiler, providing you with a user view to navigate through the hierarchy. You can utilize the GUI in Verisium to navigate the hierarchy. Given the additional performance impact, this feature is best utilized to explore the performance characteristics of individual tests/designs.

Read the next post to learn more about profile analysis.

Watch the on-demand recording of the webinar, Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator, to learn the best practices to achieve the highest performance using Xcelium Logic Simulator.