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Most have heard the phrase "time is money". Thinking more about it, probably the right phrase would be "time is more valuable than money". People look at their bank accounts with great attention but don't tend to look at their time the same way, ending up wasting this greatly valuable and important resource. You can gain money using time, but you can’t use money to purchase more time.
The “Shift Left” concept has been used increasingly within the semiconductor development flow and considered one of the primary approaches for saving time. "Shift Left" indicates tasks that were once performed sequentially while must now be done concurrently and early in the cycle leading to cost savings and accelerated time to market. Finding issues early in the RTL design flow would save weeks if not more reducing costs of late-stage RTL changes as well as avoidable iterations and cycles.
One greatly valuable place in the Design and Verification flow where "Shift left" should be adopted is the RTL Designer Signoff. However, traditional Structural Lint techniques are no longer sufficient in evaluating RTL code for today’s larger and more complex designs. Structural Lint technology needs to be significantly augmented with formal assisted technology to enable designers to catch more issues upfront and more so as true issues and not just a sea of warnings.
The Cadence® JasperGold® Superlint App is an advanced formal-based technology application that addresses register-transfer level (RTL) signoff requirements. It augments the traditional Structural Lint techniques by bringing the power of JasperGold formal technology, the leader in the formal domain with the best-in-class formal platform, to the RTL designer’s desktop. It enables designers to exercise comprehensive functional automatic checks in addition to a wide range of structural checks in the Lint and DFT domains. The JasperGold Superlint App improves design quality by reducing costs of late changes in the RTL by up to 80 percent and reducing development time by weeks when compared to existing RTL Designer Signoff solutions.
“We’ve been using the JasperGold Superlint App for more than a year, and we’ve had success with improving RTL signoff and shortening time to market. With the ability to find bugs weeks earlier in the design process, we’ve reduced late-stage RTL changes, which enables the team to save additional time when we get to the functional verification stage.”, said one of our major customers.
Remember that since "Time is more valuable than money", we should always seek for new methods and approaches to save this significant resource and the JasperGold Superlint App is definitely one of those. So I thought I'll share this good news with all our readers about an upcoming webinar on this interesting topic. Join Product Engineering Architect, Kanwarpal Singh, for a free, one-hour live webinar, ”Comprehensive RTL Signoff by Designers Using JasperGold Superlint" on June 24, 2020, where he will explain in further detail the “Shift Left” need and the capabilities of the JasperGold Superlint App which help to achieve that, along with a short demo of the same.
When: Wednesday, June 24, 08:00 PDT / 17:00 CEST / 18:00 IDT / 20:30 IST
Registration closes on Tuesday, June 23
What all will be covered?
Click here to register right away if you have a Cadence account. If not, click Register Now in the Registration Help section of the Cadence Sign In page and complete the requested information.
You can always visit the Training webpage to learn about our complete training offering.