Boost Efficiency and Performance of Simulation Acceleration Through New Rapid Adoption Kits

The state-of-the-art Palladium XP hardware/software verification computing platform unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity. As impressive as the platform is, it is equally important for those who develop these superior solutions to provide good self-help training material, as well as tutorials to reduce the learning curve, if any, in using these solutions. These materials can help users maximize the benefit from these solutions.

In this blog, I will share information on two Rapid Adoption Kits (RAKs) that I downloaded recently from Cadence Online Support. They are helping me to be productive in their related methodologies.

Cadence's RAKs help engineers learn foundational aspects of Cadence tools and design and verification methodologies using a "Do-It-Yourself", a.k.a. DIY, approach.

1. Synchronous Communication Channels for Simulation Acceleration

The acceleration environment consists generally of three major parts: the testbench, the design, and the communication channel. In a simulator, everything runs on the same engine; in simulation acceleration, the testbench runs in the simulator, the design runs in the HW accelerator, and a channel (or bridge) is required to connect the two engines to pass data and maintain appropriate synchronization. Hence, the communication channel plays a pivotal role in the overall acceleration performance.

There are various implementations of the communication channel, its characteristics, and performance considerations. The focus of this RAK is to describe the various interface options to implement the communication channel, their trade-offs, and when to apply them.

2. Compiling Large Netlists with IXCOM-based flow

The passing of netlists through tools tailored to mapping RTL is not always efficient. The sheer size of the netlist in terms of the number of files and the number of modules and design objects can stretch language compilers.

Cadence engineers have authored this new RAK, which describes the essential steps in using the simulation acceleration external netlist compile flow.

In this RAK:

• Users will understand the method to import large netlist files into the simulation acceleration flow
• Users will learn how the use of large netlists in the simulation acceleration flow, whether for ICE, STB or co-simulation, requires the generation of user data files to control the flow. With this, and a single command line option, the IXCOM-based compile flow offers efficient reuse of existing netlists to reduce the overall compile time.
• Users will leverage the concepts and example supplied in this RAK to compile their own IXCOM-based builds with large netlist files.

You can download all the Cadence Hardware and System Verfication RAKs from https://support.cadence.com/raks - System level verification and validation with Palladium XP

We will continue to provide self-help content on Cadence Online Support, your 24/7 partner for getting help in resolving issues related to Cadence software or learning Cadence tools and technologies. If you are signed up for e-mail notifications, you'll receive alerts on new solutions, application notes (technical papers), videos, manuals, etc.

Note: To access the above docs, click a link and use your Cadence credentials to logon to the Cadence Online Support https://support.cadence.com/ website.

Happy Learning!

Sumeet Aggarwal