C-to-Silicon Compiler Launch

14 Jul 2008 • 1 minute read

On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level synthesis product that improves designer productivity up to 10x in creating and re-using system-on-chip IP. C-to-Silicon Compiler enables engineers to design at a higher level of abstraction and helps automate the analysis of hardware micro-architecture.

C-to-Silicon Compiler automatically translates and optimizes abstract behavioral descriptions from C/C++ /SystemC to synthesizeable Verilog RTL for implementation, verification and SoC integration.

C-to-Silicon Compiler addresses all the major barriers to high-level synthesis adoption:

Embedded Logic Synthesis (ELS) Uses embedded RTL-Compiler for high-accuracy timing estimates that enable parallel optimization of control and datapath logic, and delivering better-than-average human QoR.
Behavior-Structure-Timing (BST) database that enables “true” incremental synthesis, avoiding the need to repeat synthesis and verification each time an incremental design-change is made.
Constraint-Functionality Separation (CFS) enables easy design-re targeting across multiple applications as well process-technologies
Auto-generated Fast Hardware Model (FHM) to accelerate verification and enable HW-SW co-development

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