Sangeeta Soni

Community Member

Blog Activity
Options

Cadence Announces PCIe 8.0 Verification IP Availability at PCI‑SIG US

• 2 minute read

At the recent PCI‑SIG Developers Conference US held on May 6-7,2026, Cadence announced the availability of its PCIe 8.0 Verification IP (VIP)—taking another significant step in enabling early, confident adoption of the PCI Express roadmap. 

As PCIe continues to evolve to meet the growing demands of AI accelerators, high‑performance computing, and hyperscale data centers, the complexity of verification grows alongside bandwidth. With PCIe Gen8 VIP, Cadence equips customers with a production‑ready verification solution aligned with emerging specifications, helping translate evolving standards into reliable silicon implementations. 

Built on a Proven, Scalable VIP Architecture 

PCI Express remains the backbone interconnect for modern compute platforms, delivering scalable performance while preserving backward compatibility across generations. Each new generation introduces architectural advances that require equally advanced verification capabilities. 

Cadence PCIe Gen8 VIP is built on the same C/C++‑based VIP architecture that has been widely adopted across previous PCIe generations and complementary interconnect standards. This architecture delivers a consistent user experience across protocols and verification environments, while enabling reuse from IP‑level verification through full SoC integration. 

The VIP supports both serial and PIPE‑based architectures and maintains protocol behavior consistency across transaction, data link, and physical layers—allowing verification teams to adopt Gen8 with minimal disruption to existing flows. 

Supporting System‑Level Verification at Extreme Speeds 

PCIe Gen8 extends the PCIe architecture to support significantly higher data rates while preserving core concepts introduced in earlier generations, such as PAM4 signaling, FLIT‑based transfers, and low‑power states. Cadence PCIe Gen8 VIP is designed to validate these capabilities across realistic system configurations. 

The VIP supports verification of root complexes, endpoints, switches, and retimers, along with monitor components for serial, pipe interface, and switch topologies, enabling customers to validate complex topologies and interoperability scenarios. Integration‑friendly building blocks, configurable checking, and coverage‑driven flows help verification teams scale from focused IP validation to full system‑level verification. 

Enhancing Debug and Productivity 

As PCIe speeds increase, observability and debug efficiency become critical. Cadence PCIe Gen8 VIP provides rich debug visibility through protocol‑aware packet tracking, waveform‑based transaction views, and trace‑file correlation across layers. 

Complemented by Cadence’s verification ecosystem—including GUI‑based configuration, reusable test suites, and automated verification planning—the Gen8 VIP helps reduce bring‑up time and accelerates convergence toward verification closure. 

Moving the PCIe Ecosystem Forward 

The announcement of PCIe Gen8 VIP at PCI‑SIG US reflects Cadence’s continued role in advancing the PCIe ecosystem—from early standards participation through customer‑ready verification solutions. 

With its combination of early availability, architectural consistency, and system‑level verification focus, Cadence PCIe VIP continues to set the benchmark for PCI Express verification, empowering customers to innovate with confidence as the industry transitions into the PCIe Gen8 era. 

  • For more info on how Cadence PCIe Verification IP and TripleCheck VIP enable users to confidently verify PCIe designs, see our product pages on  VIP for PCI Express  and Triplecheck.
  • Refer to the PCI-SIG website for more details on PCIe in general and upcoming revisions on PCIe 8.0