Cadence Introduces the Industry’s First GDDR7 Verification Solution

GDDR7 Introduction

In February 2024, JEDEC announced the successor to GDDR6 with many new features and a big leap in terms of operating speed. GDDR7 is a high-speed synchronous graphic DRAM with a semi-independent row and column command address bus and two modes of data signaling: PAM3 for high speed and NRZ for low speed. GDDR memories are used across a wide range of applications that involve high processing rates at much larger scales, such as computers, servers, data centers, etc. With ever-increasing demand for bandwidth with greater power efficiency, GDDR7 is expected to bring these capabilities to the computing world.

New Features Added in GDDR7

Clock

DRAM uses a single Write Clock (WCK) for command-address and data latching, while it generates an internal divide-by-4 clock named CK4 that is used as a reference for latencies.

Read Clock (RCK) in GDDR7 can be configured in four different modes from the mode register:

• Always running: As the name suggests, it is always running and stops during sleep modes.
• Disable: It stops running when configured in this mode.
• Start with RCKStart command: Read Clock can be started by issuing the RCK Start command before reading out data. It can be stopped using the RCK STOP command. Host can start/stop as per requirement.
• Start with Read: Read Clock automatically starts running when DRAM receives any command that involves read data out. Also, it can be stopped here using the RCK STOP command.

With the help of the last two modes, power usage can be optimized by enabling RCK only during the periods when it is needed.

Command Driving

In GDDR6, only one command can be issued at a time. GDDR7 commands are encoded in such a way that row and column commands use different bits of the CA bus. Hence, two independent commands can be issued in parallel. For example, Bank X can be refreshed by issuing a refresh per bank command on CA[2:0], while Bank Y can be read by issuing a Read command on CA[4:3] at the same time.

PAM3 Signaling

GDDR7 uses PAM encoding in high-speed operation for data, CRC, ERR feedback, and the read clock. In PAM3 mode, 256 bits of data are encoded and transferred over 8 WCK clock cycles. It significantly improves the data rate compared to NRZ while having better SNR and eye margins as compared to PAM4.

LSFR Mode of Data Training

Data training enables the host to find appropriate voltage levels and timings to transfer data reliably over high-speed data transfer. In the FIFO mode of data training, the host writes data to FIFO and reads back custom patterns. For long continuous training, GDDR7 has a new LFSR mode of training in which random training data is generated using pseudo-random bit streams. Lane masking and eye masking options are also available in the LFSR. It has error counters for each lane, which keep track of errors in write training. These can also be configured to keep track of each individual eye.

Cadence Verification Solutions for GDDR7

Cadence GDDR7 VIP supports all modes and new features as defined in the JEDEC GDDR7 specification, including a smart way to simulate the three levels of PAM3 by a real number representation.

To allow data UI simulation, Cadence VIP provides three solutions: binary bus, strength modeling, or real number modeling.

Cadence GDDR7 VIP can be integrated into various environments such as Verilog, plain system Verilog, SV-UVM, and SystemC. It has a complete set of protocol checkers and reconfigurable timers to check behavior compliance with the protocol. It supports various modes of error injection in multiple fields of transactions during array data transfer and interface training as well. It is also integrated with the waveform debugger solution to visualize transactions on the waveform viewers for faster debugging and overall verification.

With the first-to-market availability of the Cadence GDDR7 VIP, early adopters can start working with the latest specification immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure.

More information on Cadence GDDR7 VIP is available on the Cadence VIP website.

If you have any queries or questions, please contact us.