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Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the most complex challenges faced by verification engineers. Over the years, it became even more challenging with increasing number of cores in CPU clusters and introduction of the embedded L3 (level 3) cache to the coherent interconnect devices. Advent of inter-chip coherency with the new CCIX (pronounced see-six) protocol elevates this challenge to a whole new level. The basic idea behind CCIX, is to define a single coherent infrastructure for multiple SoCs such CPUs, GPUs, and Accelerators.
CCIX is a layered protocol with Protocol Layer being responsible for coherency aspects and Transport Layer being responsible for transporting CCIX transactions between participating chips. Since the CCIX Transport Layer uses modified PCIe protocol as a communication infrastructure, engineers tasked with validation of CCIX based systems have to deal with challenges of Transport Layer verification in addition to already formidable challenges of coherency verification.
To address various aspects of CCIX validation and speed up the verification process, engineers require a powerful tool set which could be flexibly applied to various CCIX topologies and Designs Under Test (DUTs). Such a tool set should include verification IPs (VIPs) for CCIX Protocol and Transport Layers as well as an intelligent scoreboard for system-level coherency verification. Each VIP in the tool set must deliver three major capabilities. They are:
Cadence CCIX verification tool set includes several flexible verification solutions working in concert.
The following block diagrams depict a few typical application cases of Cadence CCIX verification tool set.