CDNLive paper: High-level Synthesis on Video Processing ASIC

The proceedings from the recent CDNLive! event in Israel recently became available, and you can access them with your Cadence.com account login.

The paper entitled "High-level Synthesis on Video Processing ASIC" delivered by Yaniv Fais and Michael Zarubinsky of Freescale gives a great look into their group's adoption of C-to-Silicon Compiler high-level synthesis and their application of it on a video accelerator.

For anyone considering a move from RTL-based design up to SystemC-based, it is a must-read. First it highlights the benefits of moving up in abstraction through a simple example, showing how you can quickly explore different micro-architecture implementations for a simple code snippet. Then it goes on to show a code sample from their project and how they explored their options using the C-to-Silicon GUI, for example:

• Highlighting the critical path in the control-dataflow graph (CDFG)
• Using the critical path viewer to see the actual instance-level timing from embedded RTL Compiler
• Viewing the overall performance of the algorithm via simulation vectors with SimVision
• Exploring the area tree map to look for opportunities to recover area where there is plenty of timing slack

The paper finishes with a nice summary of the benefits as well as a balanced look at the challenges they faced in evolving their methodology to a higher level of abstraction. Suffice to say, their experiences align with other customers we have heard from at our most recent C-to-Silicon user group in Japan and the recent DAC panel on high-level synthesis.

And to hear these types of papers presented in the future and to be able to speak directly to customers that have been through these experiences, register for a local CDNLive! conference:

 http://www.cadence.com/cdnlive/pages/default.aspx

-Jack Erickson