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On November 28, 2017, Cadence announced the release of the first available PCIe® 5.0 Verification IP. This new VIP gives designers access to Cadence’s TripleCheck technology—which gives designers a comprehensive verification plan that uses measurable objectives related to spec features, along with a test suite containing thousands of tests. These combine to greatly improve the speed and quality of functional verification runs for server and SoC designs using the PCIe 5.0 specification. It also gives designers access to the Indago Protocol Debug App.
The ferocious appetite for higher performance demanded by Big Data, IoT and mobile computing is being addressed with the fast tracking of the PCI Express 5.0 specification by PCI SIG. Early adopters have already been working on PHYs beyond PCIe Gen 4 16GT/s speeds and will be able to quickly move forward with Gen 5 support as the spec solidifies at this accelerated pace with rev 0.7 anticipated for Q2 of 2018.
“Our team has successfully utilized the Cadence VIP for previous versions of the PCIe specification, which enabled us to deliver world-leading interconnect solutions for compute and storage infrastructures,” said Shlomit Weiss, the senior vice president of silicon engineering at Mellanox Technologies.
The Cadence VIP with TripleCheck is part of the Cadence Verification Suite, and optimized for Xcelium Parallel Logic Simulation.
To read the full press release, check here, and to read more about TripleCheck for PCIe 5.0, check here.