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uvm
Functional Verification
webinar
Duolos
uvm register layer

Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

12 Sep 2018 • Less than one minute read

Join us on September 14th for a free one-hour webinar on the finer aspects of the UVM register layer. We’ll be focusing on key aspects of the UVM Register Layer that can help you with your UVM modeling in ways you may not be aware of.

We’ll be covering the following topics:

  • How to use user-defined front doors and back doors to expand what the register layer can do
  • Understanding the role played by the predictor, and how to use it with the aforementioned user-defined front doors
  • Using register callbacks to help model quirky register behaviors, alongside the side-effects of register read/writes
  • What changes you can or can’t make to UVM code while preserving the random stimulus generation.

Combined, the information covered in these topics can make you a better user of the UVM register layer. Code examples shown during the webinar can all be run with our Xcelium Parallel Simulator.

Come join in!

For more information on this webinar, and for available times on September 14th, check out the link here.

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