Rapid Adoption Kit (RAK) -- Creating UVM Verification Environments with Hardware-Assisted Verification

The hands-on, learning-by-doing, trying, discovering, failing and learning approach is not unique. John Dewey initially promoted the idea of "learning by doing." Teams within Cadence took this idea and uniquely developed a new content type, the Rapid Adoption Kit (RAK), in 2011. 

The RAK is a package of different knowledge pieces (presentations and application Notes along with a demo design database with relevant scripts and instructions) to demonstrate how Cadence customers can improve their productivity and maximize the benefits of Cadence tools and technologies. A self-packaged testcase can be downloaded to "play around" with a particular feature or capability of the tool without active support.

Very recently, Cadence Sr. Staff Application Engineer Dan Cohen and Staff Application Engineer Per Edstrom developed a Rapid Adoption Kit, first in upcoming series, which is geared for users doing simulation acceleration and in-circuit emulation with the Palladium XP family of products.

System level verification and validation with Palladium XP

Raj Mathur, Sr. Product Marketing Manager at Cadence, reviewed this RAK and noted that with growing design and verification complexity taxing the simulator engines, the need to accelerate UVM based simulation using hardware assisted verification is compelling. These Rapid Adoption Kits are geared for UVM community members interested in learning how to create UVM verification environments that are conducive to acceleration with hardware assisted verification products such as Palladium XP. Raj further elaborates that these kits also aim to show you how you can architect your UVM verification environments to achieve optimal performance. They are kept up-to-date with the current release of the software and updated according to user feedback.

You can view presentations, application notes, and/or download the package that contains presentations, application notes, lab exercises, relevant scripts and instructions.

This UVM Acceleration (Core) RAK's goal is to help you generate verification environments that simulate quickly in Incisive and Palladium, while using the standard UVM library and techniques to provide reusable, scalable verification environments. This RAK uses exactly the same environment in Incisive and Palladium ensuring there is only one development stream to manage.

We are also covering the following technologies through our RAKs at this moment:

Synthesis, Test and Verification flow
Encounter Digital Implementation (EDI) System and Sign-off Flow
Virtuoso Custom IC and Sign-off Flow
Silicon-Package-Board Design
Verification IP
SOC and IP level Functional Verification
System level verification and validation with Palladium XP

Please keep visiting https://support.cadence.com/raks to download your copy of the RAK.

We will continue to provide self-help content on Cadence Online Support, your 24/7 partner for getting help in resolving issues related to Cadence software or learning Cadence tools and technologies. If you are signed up for e-mail notifications, you've likely to notice new solutions, Application Notes (Technical Papers), Videos, Manuals, etc.

Note: To access above docs, click the relevant link and use your Cadence credentials to logon to the Cadence Online Support - https://support.cadence.com/ web site.

Happy Learning!

Sumeet Aggarwal