• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Verification
  3. CtoS support of Multiple Clocks
TeamESL
TeamESL

Community Member

Blog Activity
Options
  • Subscribe by email
  • More
  • Cancel
High-Level Synthesis
CTOS
clock
System Design & Verification
SystemC
C-to-Silicon Compiler
clocking

CtoS support of Multiple Clocks

20 Apr 2009 • Less than one minute read
In a previous blog entry we discussed C-to-Silicon’s (CtoS’s) ability to support multiple threads in a similar way that traditional Hardware Description Languages (HDLs) support multiple processes.

There are many applications, such as multi-rate DSP applications, in which it is not only necessary to describe the circuit as multiple concurrent threads but also that  these threads operate on different clock domains.

Multiple clocks are fully supported by traditional RTL based synthesis tools and therefore must also be supported by any viable ESL High Level Synthesis alternative.

SystemC and CtoS support multiple clock domains. Each thread declared inside an SC_MODULE can be clocked by a separate clock signal.

By supporting multiple threads and multiple clocks SystemC and CtoS provide a viable alternative to the traditional RTL Synthesis approach. This support is usually not provided by a pure C / C++ High Level Synthesis approach.

 
This Team ESL posting is provided by Dr. Sergio Ramirez, Sr Staff Product Engineer for the C-to-Silicon Compiler high level synthesis product. Product Engineer for the C-to-Silicon Compiler high level synthesis product. 

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information