DAC 2014—ESL Design Is Dead... Long Live ESL!

27 May 2014 • 20 minute read

Next week the EDA industry is getting together in San Francisco for Design Automation Conference 2014. As I pointed out in a recent blog called "Confessions of an ESL-Aholic", the scope of electronic system level (ESL) design has changed quite a bit over the last 15 years, but there is still a lot of promise, and a lot to come. The basic premise of my soberness on classic ESL is that the basic momentum upwards in abstraction continues—as indicated in my graph dated ca. 2001 below—raising the level of abstraction from transistors to gates to RTL and inevitably above RTL.

A tale of inevitability—Raising levels of abstraction (ca. 2001)

However, a lot of the decisions that 15 years ago I thought would be based on more abstract representations, today require even more accurate representations like RTL. In addition, matters of practicality lead a trend against fully complete models at the transaction-level, but instead drive hybrids of virtual platforms at the transaction-level combined with RTL either in simulation, emulation, or FPGA-based prototyping.

As we gather in San Francisco, we are joined by an increasing number of software developers. Software has simply become too important as part of the overall chip and system development, both in defining the actual functionality, as well as becoming a central part of the verification process. Because ARM is a key ecosystem partner for embedded software, I have summarized the ARM-related events in a blog on the ARM Community website.

My dance card for DAC is pretty full—as you can see below a list of system-development-related activities that my team and I have prepared for this DAC. ESL will be at the core again, but as I pointed out in my "confession" blog, there will be a lot more links to implementation. Before you jump to the table with all the links below, here are my highlights and thoughts:

Why am I still an ESL-aholic? Well, for one, software changes the complete mix as indicated in my abstraction graph above. Also, as you will see in presentations from National Instruments, Intel, and Methods2Business, there are exciting developments going on two major fronts. First, we are working hard on raising the level of abstraction with high-level synthesis and bringing it closer to virtual prototyping with a unified entry and more automation. Second, as NI's George Zafiropoulos will show, there are exciting opportunities to unify system development pre- and post-silicon. In addition, you will hear from our partners Xilinx and DINI with their views on the FPGA world—obviously key to system design, as well.
Why do we need to stay connected to implementation? In our Cadence Theatre, you will see NVIDIA on their v8 software development work, CSR on how they accelerate software development, AMD on application-level low-power event monitoring, Solarflare on running a 10G/40G NIC on Palladium and RPP, as well ARM on graphics software development. What do they all have in common? They are all using combinations of the System Development Suite engines, be it VSP and Palladium XP to combine virtual prototyping and RTL execution, or using tools serially taking advantage of the flow congruency we have implemented for emulation and FPGA-based prototyping. We will also have a dedicated 90-minute tutorial on similar topics for ARM-based design on Monday, joining forces with ARM and Netspeed.
How do I connect to system environments? It is a broad range, from fully virtualized to real physical connections, and all have their place. Some of the above presentations will touch on that, but specifically check out the presentations we will give at the Cadence Theatre based on a presentation Samsung gave at CDNLive (Validating complex multi-core designs while optimizing HW/SW performance), as well as different use models for Accelerated Verification IP as used by AMD, NVIDA, and Broadcom (Accelerated VIP, a Deep-Dive Based on Customer Case Studies).
Why does this ESL-aholic still love this field? You can hear all about the Shift to Software-Driven Verification during our Breakfast Panel moderated by Brian Fuller on Tuesday morning, bringing together a stellar cast of panelists including Victor Tirva, Microsoft, John Goodenough, ARM, Alex Starr, AMD, Jim Hogan, Vista Ventures, and Mike Stellfox, Cadence. I will be on several panels myself, both on Wednesday. Firs,t I will join a discussion on Internet of Things Design Concerns, together with Jim Hogan, Bernard Murphy, Atrenta, Gary Smith, GSEDA, and Randy Smith, Sonics. Then later on Wednesday, I will participate in an automotive panel, System Engineering Methods and Tools for Automotive EE Design: Old Wine in a New Bottle, together with Jim Kapinski, Toyota, Khurshid Qureshi, Dassault Systèmes, Sethu Ramesh, General Motors, and Jochen Haerdtlein, Robert Bosch. Where else could I be involved that closely in such diverse, yet connected topics?
Where to dance? Yes, this German loves to dance and has (some) photos to prove it J The two opportunities this DAC that I won't miss are Jim Hogan's party at Slim's on Monday night—go join and donate, it is for a great cause of helping children who've been abused—as well as the Denali Party by Cadence on Tuesday night.

And yes, I will try to sleep in on Thursday... See you at DAC 2014 in San Francisco.

Here comes the full list, sorted by time:

Sunday, June 1
5:00pm	“The New World of Electronics”, DAC Welcome reception with Gary Smith discussion of market trends, Grand Ballroom A, Intercontinental Hotel This year's talk will focus on how the world of electronics is changing dramatically. This is having a severe impact on the semiconductor companies. Their response is causing major changes in the EDA industry. The annual EDA forecast also will be shared.
Monday, June 2
10:30am to 12:00pm	Tutorial: Optimizing ARM-Based SoCs for Performance and Speeding System Validation Design of multi-core systems requires a sophisticated approach to architecture of the SoC, and a thorough methodology for embedded software development. Ensuring that expected performance targets are achieved is becoming more and more difficult due to the number of processors and the expanding configuration choices of system interconnect. Developing hardware and software in parallel is often facing significant barriers: suitable models for all the IP blocks may not be available and when they are available then they may be in RTL only, lacking corresponding transaction-level models. In this tutorial we will address methodologies for performance analysis of advanced ARM interconnect, as well as approaches of hybrid execution for software bring-up, linking abstract simulation models with more detailed models of IP to create a hybrid simulation platform. The exploration of these topics will be illustrated through use of a case study where this approach has been utilized in practice.
	Poonacha Kongetira, NetSpeed Systems, San Jose, CA Robert Kaye, ARM Ltd., Cambridge, United Kingdom Nick Heaton, Cadence Design Systems, Inc., San Jose, CA Frank Schirrmeister, Cadence Design Systems, Inc., San Jose, CA
	Room 304
12:30am	Post Silicon Validation and Pre Silicon Verification—Leveraging the Best of Both Worlds
	George Zafiropoulos, National Instruments
	Cadence DAC Theatre
1:30pm	Palladium/VSP ARM v8 Tegra Hybrid for Pre-Silicon Android Validation and Open GL Graphics Testing
	Vikramjeet Singh, NVIDIA
	Cadence DAC Theatre
3:00pm	Industry-leading solutions for FPGA-based prototyping
	Kirk Saban, Xilinx
	Cadence DAC Theatre
4:00pm	Application-level power event monitoring using hybrid emulation technique
	Alex Starr, AMD
	Cadence DAC Theatre
5:00pm	Accelerating Embedded Software Development with the Cadence Rapid Prototyping Platform
	Juergen Jaeger, Cadence
	Cadence Booth, Demo Suite, Sign up here
Tuesday, June 3
8:00am (Doors open at 7:30am)	Breakfast Discussion moderated by Brian Fuller: The Shift to Software-Driven Verification
	Room 104 at the Moscone Center, located in front of Exhibit Hall B Register here
	Jim Hogan, Industry Luminary, Vista Ventures Victor Tirva, Director, Microsoft John Goodenough, VP Design Technology and Automation, ARM Alex Starr, Fellow, Virtual Bring-up Architect, AMD Mike Stellfox, Fellow, Cadence
	Waiting too long to integrate hardware and software has proven to have disastrous results. The development, integration, and verification of complex hardware/software systems is demanding a “shift-left” into the pre-silicon phase of tasks that traditionally have been done after silicon has become available. From the early stage of transaction-level modeling- (TLM-) based development through RTL-based development, software has become an important part of the verification process. This session will introduce the challenges design teams are facing. The speakers will also discuss some key user experiences on how verification is shifting and how EDA tools are enabling that shift.
11:30am	Top-Down Design Methodology with CoFluent™ Studio and High-Level Synthesis
	Laurent Isenegger, Intel – CoFluent
	Cadence DAC Theatre
11:30pm	Accelerating Embedded Software Bring-Up and Verification for ARM-Based Designs
	Frank Schirrmeister, Cadence
	Samsung Booth 819
1:00pm	Emulating a dual-port 10G/40G NIC on Palladium and RPP
	Ken Huang, Solarflare
	Cadence DAC Theatre
1:00PM	ARM v7- and v8-Based Accelerated System Development
	Frank Schirrmeister, Larry Melling, Mike Stellfox, Cadence
	Cadence Booth, Demo Suite, sign up here
1:30pm to 3:00pm	CoMix – The Concurrent Model Interface for the Parallel Simulation of Loosely-Synchronized Many-Processor Platforms
	Christian Sauer, H-M Bluethgen, H-P Loeb, Cadence, Munich, Germany Eric Frejd, Ericsson, Kista, Sweden
	Room 105
2:00pm	Accelerating Graphics Software Simulation in Virtual Platforms
	Rob Kaye, ARM
	Cadence DAC Theatre
3:00pm	Validating complex multi-core designs while optimizing HW/SW performance
	Raghu Binnamangalam, Cadence/Samsung
	Cadence DAC Theatre
5:00pm	What’s New with the Palladium XP Series
	Michael Young, Cadence
	Cadence Booth, Demo Suite, Sign up here
Wednesday, June 4
9:30am	SystemC-Based Design for Next Generation of Wi-Fi 802.11n MAC IP
	Marleen Boonen, Method2Business
	Cadence DAC Theatre
10:35am	Early OS Bring-Up for ARM-Based Systems
	Frank Schirrmeister, Cadence
	ARM Booth 2001
11:00am	ARM v7- and v8-Based Accelerated System Development
	Frank Schirrmeister, Larry Melling, and Mike Stellfox, Cadence
	Cadence Booth, Demo Suite, Sign up here
11:00am	Accelerated VIP, a Deep-Dive Based on Customer Case Studies
	Ian Nixon, Cadence with AMD, Broadcom, and NVIDIA
	Cadence DAC Theatre
12:00am	Hardware Solutions for FPGA-Based Prototyping
	Mike Dini, DINI
	Cadence DAC Theatre
1:00pm to 2:15pm	Panel Discussion: Challenges of Building the Internet of Things
	Room 252/254/256, DAC at Moscone Center
	Jim Hogan, EDA/IP’s pre-eminent industry visionary and investor Bernard Murphy, CTO, Atrenta Frank Schirrmeister, Group Director, System Development Suite, Cadence Gary Smith, Market Analyst, GSEDA Randy Smith, VP of Marketing, Sonics
	We all know the IoT is coming. But how will it affect EDA/IP technology and what do we need to do to provide tools and technology for these IoT device designers?
1:00pm	What’s New with the Palladium XP Series
	Michael Young, Cadence
	Cadence Booth, Demo Suite, Sign up here
1:30pm	Using Palladium/VSP Hybrid to Accelerate SW Development
	Moshe Berkovich, CSR
	Cadence DAC Theatre
4:00pm	Accelerating Embedded Software Development with the Cadence Rapid Prototyping Platform
	Juergen Jaeger, Cadence
	Cadence Booth, Demo Suite, Sign up here
4:00pm to 6:00pm	Panel Discussion: System Engineering Methods and Tools for Automotive EE Design: Old Wine in a New Bottle?
	Room 309
	Jim Kapinski, Toyota Motor Corp., Gardena, CA Khurshid Qureshi, Dassault Systèmes, Dearborn, MI Frank Schirrmeister, Cadence Design Systems, Inc., San Jose, CA Sethu Ramesh, General Motors Company, Warren, MI Jochen Haerdtlein, Robert Bosch GmbH, Stuttgart, Germany
	Whether existing design methods and tools from the embedded system domain could be directly applied to automotive systems engineering or new techniques specifically tailored for automotive systems are required is a topic of constant debate. This panel brings together experts from OEMs, Tool Suppliers and EDA companies to discuss this topic.
Thursday, June 5
3:30pm to 5:00pm	Panel Discussion: Designing In Security: What Will It Take?
	Room 309
	Robert Nguyen, Intel Corp., Santa Clara, CA Ron Perez, Advanced Micro Devices, Inc., Austin, TX Mohit Arora, Freescale Semiconductor, Inc., Austin, TX Fedor Pikus, Mentor Graphics Corporation, Wilsonville, OR Jim Ready, Cadence Design Systems, Inc., San Jose, CA
	The security and trustworthiness of everything from large-scale servers in the cloud to the lock on a hotel room are of growing concern. With the proliferation of intelligent, networked devices and systems, the “hardware root of trust” is a vital component of overall security. A panel of industry experts will provide perspectives on the challenges to development and adoption of strategies and techniques for Designing In Security, and research that is needed to accelerate progress. A new industry consortium on Trustworthy and Secure Semiconductors and Systems (T3S) that is partnering with government to support fundamental research also will be discussed.