• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Verification
  3. DAC Virtual Platform Workshop
jasona
jasona

Community Member

Blog Activity
Options
  • Subscribe by email
  • More
  • Cancel
DAC
virtual platform
embedded software
metric-driven verification

DAC Virtual Platform Workshop

30 Jun 2009 • 1 minute read

Back in early May, I wrote that it was Not Too Early to Start Thinking About DAC 2009. Well, now it is too late to start thinking about it, and it is time to start acting by making plans to get to San Francisco.

One of the events I will attend is the Virtual Platform Workshop.  Workshop organizer Soha Hassoun recently posted an article on Gabe on EDA that raises some interesting questions. Trying to blend the world of chip design with embedded software is a topic that comes up over and over for conferences. It seems every semiconductor company is going in this direction, and I have covered the topic in many of my blog posts here on cadence.com. Software engineers are probably not naturally drawn to attend DAC, but on the other hand we need some good attendance to demonstrate that engineers are interested in topics that blend the hardware and software disciplines. There is a great opportunity for verification engineers to make the jump from RTL simulation and drive the next level of verification at the Virtual Platform level. Experts are needed to understand modeling techniques, Virtual Platform assembly, mixed hardware/software debugging techniques, system level verification methodologies, and more. The ability to construct and utilize Virtual Platforms for verification by bringing them to embedded software engineers to improve overall system quality is an excellent topic to research at DAC before heading home with new ideas to improve verification. After all, the Virtual Platform is really a verification tool. In a sense, it's just a simulator, and using it to run embedded software is just another way to do verification by finding bugs or proving there are no bugs. Hardware stimulus and checking are still required as well as all of the metric-driven flows used today in hardware verification.

I'm sure you will be soon overwhelmed with information about DAC. Good luck sorting though it, and make sure to come out and support all of the Virtual Platform related activities at DAC. This is a great conference to interact with other engineers on the topic and there will be plenty of ways to do it during the week.

Jason Andrews

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information