DAC 2012: Enabling the Programming of an Extensible Processing Platform

We at Cadence have been writing about the virtual prototype associated with the Xilinx Zynq-7000 Extensible Processing Platform (EPP) quite a bit. At the recent Design Automation Conference (DAC) it was our pleasure to welcome Dave Beal from Xilinx in the EDA360 Theatre to talk about Zynq, its programming, and the virtual prototype Cadence co-developed with Xilinx.

Dave started off with defining a virtual prototype as applied to the Zynq-7000. A virtual prototype encapsulates and models hardware, firmware, and interface details to allow software to run at the hardware/software boundary interface. It models an embedded platform, real or envisioned, and executes the same software binaries as the actual hardware. A virtual prototype is generally comprised of functional models which are functionally accurate but are not typically timing/cycle accurate. It also may be extended with real HDL or RTL.

Dave used the following graphic to illustrate the hardware software stack a user may be interacting with when using a virtual prototype:

Hardware and firmware are combined into a model representing the device. It is presented to the operating system device interfaces on which the actual operating system resides, and on which the actual applications are written.

Dave continued to describe how FPGAs change the requirements for virtual prototypes, which have been available for several years for off-the-shelf development boards, and for off-the-shelf system boards like ATCA and custom designs created by dedicated modeling teams. Now, FPGAs by definition enable engineers to customize the silicon. As a result, virtual prototypes must be easily customizable too. Designs consist of off-the-shelf IP cores and custom IP, so a virtual prototype must be extensible to support a combination of existing HDL/RTL and functional models.

How much can a virtual prototype reduce time to market? The answer was a clear "It depends." Specifically it depends on the size of software team waiting on engineering specialists, the amount of customization required and the hardware development effort vs. model development effort. Dave introduced a rule of thumb that models typically take from 25% to 5% of the time required to create the actual hardware design. The full benefit to users will become clear by a project plan comparison with/without a virtual prototype. In doing so, Dave concluded that virtual prototypes add a new, independent and parallel software development path pre-hardware, pre-firmware and pre-RTL, and therefore significantly accelerates application development and time to market.

What I especially liked about Dave's presentation was his characterization of five use models he sees as a good or bad fit for virtual prototypes:

• 1. System Exploration and Prototyping: A virtual prototype provides an executable system in which different HW/SW partitioning schemes can be prequalified based on processor work load. Users can run real operating systems and application code with high-level models and observe processor usage statistics (using native OS utilities) as the function is moved from processor to accelerator. With this they can gain a high level understanding of reserve processing power for each configuration. For exploration, the question of accuracy is an often discussed topic. Dave concluded that although the result is not a detailed analysis, it is useful to determine which approaches warrant further, more detailed investigation.
• 2. Software Development and Debug: Any application using processor instructions, operating system APIs, or device registers and memory addresses can be developed and debugged efficiently. Virtual prototypes provide hardware functional equivalence for the processor instruction set to program against as well as the board and device functionality. This enables software development before the boot loader, RTL or the hardware are available.
• 3. System Integration and Test: Earlier system integration simply means reduced risk. Virtual prototypes can provide what Dave called "Better Than Hardware" Corner Case Testing, because a virtual prototype offers unlimitedfault injection. Specifically, the virtual prototype gives users visibility and fault injection to literally every aspect of the system. Software and hardware parameters and attributes can be methodically modified for test cases and system software responses can be exercised in ways that are otherwise impossible. So while the final system integration and test is performed with actual hardware and firmware, early integration using a virtual prototype simply reduces risk.
• 4. Firmware Development: Dave stated that virtual prototypes are not typically suited to a wide range of firmware development. Dave's rule of thumb was that if a developer uses a logic analyzer then a virtual prototype is not a good fit! To me this depends on the definition of firmware and I had a discussion on this with Dave afterwards. For Dave, functions performed by the firmware are often used to define the functional model, which results in a circular dependency. I think this may simply be a hierarchy situation - I have seen even low level boot code developed using virtual prototypes. But if firmware is defined as "extending the hardware functionality," then it most certainly may not be accessible or even visible to the user of that function. We'll discuss more and let you know. For Dave, virtual prototypes do eliminate development dependencies on firmware for a sub-system, for which the functional model is the combination of hardware and firmware. The functional device model can be created before firmware is complete and the virtual prototype start-up scripts initialize devices to their post-boot state. Once that is done, OS, driver and apps development can start before firmware and boot loader are available
• 5. Performance Optimization: Virtual prototypes are not typically suitable for performance optimization; again, Dave's rule of thumb was that if a software developer uses a logic analyzer then a virtual prototype is not a good fit! Specifically, performance optimization involves coding for hardware attributes such as bus timing or cache hit/miss. If those are added to the virtual prototype, then some of the speed advantages go away. Dave said that virtual prototypes are very useful to quickly bring the software to a functional and "nearly complete" state and to make it ready to be optimized on physical hardware. This is no different from hardware-only development.

I have to agree with this characterization of virtual prototypes, barring the discussion with Dave whether or not "firmware extending hardware functionality" is simply a hierarchical effect of sub-systems with firmware integrated together, while the firmware on the sub-system is still applicable for development on virtual prototypes.

To close, my absolute favorite take-away from Dave's presentation was the slide titled "Virtual Platforms Offer Unmatched Capabilities - Even After Hardware is Available." This has been an issue virtual prototype providers have been battling for a long time - is there value after silicon is available? Well, according to Dave there is.

Virtual prototype software development capabilities are unmatched by real hardware. Users have complete control over time by stopping and resuming the system - every clock, bus and I/O -- and doing advanced full-system logging. Virtual prototypes also provide advanced debugger and system analysis tools, multicore debugger and post-run debug, hardware break/watch points, the ability to view and modify every register, as well as logic analyzer capabilities for viewing hardware signals and model transactions. Overall the virtual prototype's tools should make development and debug easier than is possible with real hardware!

By the way, you can see Dave Beal from Xilinx talk about virtual prototypes here. I'll let you know how my discussion with Dave on the definition of firmware goes ...

Frank Schirrmeister