Day 1 of DAC is a Wrap

28 Jul 2009 • 3 minute read

Well, it was a half day at DAC for me as I suffered a 2 hour flight delay from Minneapolis to San Francisco. It seems the fine Northwest aircraft I was on suffered a tripped circuit breaker that led to a relay that had to be replaced. I'm not convinced the aging bird doesn't have vacuum tubes inside somewhere. I guess I should be more appreciative of the fact that I can cover the 1586 miles by sitting in a chair for 3 1/2 hours and flying like a bird, when only 100 years ago it would have taken months or years to get from Minnesota to California.

This afternoon I attended the 11th NASCUG Meeting, that's the North American SystemC User's Group. Overall, it was a useful update on the state of SystemC mixed with some relevant user experiences.

During the Interactive Town Hall Meeting I was pondering the relationship between the OSCI proof-of-concept simulator, a free implementation of SystemC that seems to be used by many of the presenters, and the fact that SystemC is an IEEE standard. I also linked this thought to a recent post about a discussion about what should be free. Maybe the simulator should be free, or maybe the IP models used in Virtual Platforms should be free, or maybe everything should be free!

Here are some things to think about, as always comments are encouraged:

How much of the success of SystemC is because of the free OSCI simulator?

Anecdotally, It seems most people are very grateful for the OSCI simulator, but other languages like Verilog and VHDL are pretty successful without providing a free simulator (I don't really count Icarus Verilog because it came after most people already had a simulator they paid for).

How much of the success of SystemC is due to the standardization of IEEE 1666?

Certainly, standards can cause markets to take off. Users want to avoid the dreaded "vendor lock-in" and standards provide reuse across vendors. We have seen this recently with the growth of OVM, the Open Verification Methodology. The standardization of e as IEEE 1647 came after the language was already very successful and seems to have contributed less to avoiding vendor lock-in, but some changes may be in the works.

Over the last 5 to 10 years we have witnessed the almost complete commoditization of the operating system and many software development tools. At DAC 1998 in San Francisco I bet most demos were running on Sun hardware with the Solaris operating system. Today, at DAC 2009 in San Francisco I bet most demos are running on x86 hardware with Linux as the operating system. Many have pondered over and over what this means and how to operate successful companies within the environment of free software. Articles such as Five Open Source Business Models about open source business models are numerous, and most are hard for me to understand how they can be successful (even Red Hat).

This brings us to ponder what should be free in the SystemC and Virtual Platform area. There are three general areas:

Simulator
Models
Debug, Verification, and Analysis tools

Potentially, nothing could be free, but it might hinder the growth of SystemC as a basis for Virtual Platforms (besides the fact that OSCI is already free and it's probably too late to go back). Potentially, the models could be free because IP vendors want to spread the use of their IP and a model is not enough to make any silicon and users will need to pay for the rights to make chips anyway. Many customers also feel they pay enough for the licensing rights to make chips, so charging extra for a model is somewhat insulting. Similarly, FPGA vendors often give away tools to get users to use their FPGAs because in the end they will need to buy chips. Maybe even tools like better debuggers (better than gdb) or verification tools and analysis tools for Virtual Platforms could be free, but if everything is free the entire ecosystem will likely collapse since nobody likes to work for free.

From the Selling Free Stuff article we can conclude Imperas would like to have free models and sell simulation and tools, and Synopsys would like to sell models. Cadence has always had an excellent simulator and has been steadily adding better tools for SystemC and TLM2, and more recently adding new model support to fill this gap.

There definitely seems to be momentum in the industry about SystemC and TLM2 for Virtual Platform, and only time will tell how the different approaches turn out.

Jason Andrews