DFI 6.0 Key Highlights of the Latest DFI Specification

The DDR PHY Interface (DFI) protocol specifies the signals, timing parameters, and configurable options necessary for the transfer of command information and data across the DFI, facilitating communication between the DDR memory controller (MC) and the DDR PHY (PHY). Programmable parameters are system-defined or provided by either the MC or PHY and are set within the MC and/or PHY as required. The DFI 6 protocol is applicable to DDR5, DDR5 RDIMM, DDR5 LRDIMM, DDR5 MRDIMM, LPDDR5, LPDDR6, and HBM4 DRAM technologies.

DFI 6.0.1 (also referred to as DFI 6.0 in the rest of the blog) is the latest standard of the DFI specification. It removes support for earlier DDR/LPDDR generations, adds support for LPDDR6 and HBM4, adds/modifies low-power features, reorganizes WCK and memory-error handling, removes the disconnect protocol, and adds support for 1:3 and 1:6 DFI ratios.

Highlights of the DFI 6.0 standard (as compared to DFI 5.2):

Supported Memory Standards

DFI 6.0 narrows the legacy scope and re-centers the specification on newer memories, while adding explicit support for LPDDR6 and HBM4. DFI 6.0 also removed DDR/2/3/4 and LPDDR/2/3/4 support that were supported until DFI 5.2 specification.

DFI 6.0 includes LPDDR6 and HBM4 while describing various DFI bus operations like CA bus mapping, functional-use sections, and figures for specific device timing. 

Command Bus Signal Naming Change

The command/address signaling was updated in DFI 6.0 from a dfi_address in v5.2 to a dfi_cmdaddr to better align with the current protocols. There is no functional impact of this change. While DFI 5.2 describes CA mapping onto the dfi_address bus, including detailed mapping text for LPDDR2/3/4/5 and DDR5, in DFI 6.0, the contents and functional timing examples refer to mapping the CA bus to the dfi_cmdaddr bus, and the LPDDR6 timing figures explicitly use dfi_cmdaddr fields such as dfi_cmdaddr_p0[3:0] and dfi_cmdaddr_p1[3:0]. DFI 6.0 also adds command bus enable dfi_cmd_en, to allow selective command sampling that can be used for runtime power optimization for command path.

Disconnect Protocol Removed

DFI 5.2 includes support for the “disconnect protocol” that can be used to break up a handshake between two DFI signals. This information is conveyed through the dfi_disconnect_error signal. DFI 6.0 doesn’t have any explicit “disconnect protocol”. However, DFI6.0 does allow using existing handshake signals in a different way to allow for ending early.

Error Handling Reorganized and Expanded

DFI 6.0 presents error reporting in a more explicit memory-oriented structure than DFI 5.2.  DFI 5.2 specification includes an “error interface” and an “error signaling” section. 

In DFI 6.0, the contents include “memory errors/interrupts” under the command interface and a dedicated “memory error/interrupt reporting” chapter with explicit examples for dfi*errmode = 0 and dfi*errmode = 1, as well as command, write-data, and read-data error timing parameters.

Low-Power and Sleep Enhancements

The DFI 6.0 added and modified low-power features. DFI 6.0 adds explicit top-level status and functional use sections for sleep, including “sleep request protocol,” and specifically calls out corrections to the frequency change and sleep protocols. DFI 6.0 also removed the disconnect protocol from all handshakes

By contrast, 5.2 has low-power-control handshaking and frequency-change sections, but it does not have a standalone top-level sleep section in the table of contents. 

Frequency Ratio Support Expanded

DFI 5.2 matched-frequency and frequency-ratio systems include 1:2, 1:4, or 1:8 ratios, and their figures show 1:2 and 1:4 phase definitions. DFI 6.0 added support for 1:3 and 1:6 DFI ratios. All ratios are optional, and what is supported is an implementation decision.

Data Path Extensions

DFI 6.0 adds new capabilities to data path, which includes:

• Write data parity (HBM4)
• Read data parity along with valid separation (HBM4)
• Data severity signaling (rddata_sev) (HBM4)
• Expanded ECC coverage (HBM4 + LPDDR6)

These improvements align with the reliability requirements for HBM4 and LPDDR6-based memory subsystems.

Legacy 3DS Content Removed with Older DDR Support

DFI 5.2 contains a dedicated “3DS stack support” section, including “3DS addressing with dfi_cid and dfi_cs for DDR3” and “for DDR4.”  DFI 6.0 no longer supports dfi_cid and dfi_cs pins as the standard removes DDR3 and DDR4 support. 

Here is a tabular summary of the differences between DFI 5.2 vs DFI 6.0 standard:

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Reach out to Cadence Verification IP experts at talk_to_vip_expert@cadence.com  

More information on Cadence DFI VIPs is available at Cadence VIP DFI VIP Website, and Cadence's offered memory models can be found at Cadence Memory Model Website.