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Before a video frame can be sent, the Source (DP-TX) must complete link training (LT) with the downstream devices. DisplayPort (DP) version 2.0 specification mandates support for a 128b/132b link layer and non-transparent Link Training-Tunable PHY Repeater (LTTPR) device when connected.
The diagram below shows the connection between the source, LTTPRs, and sink devices. The specification allows up to eight LTTPRs. The DP-TX trains each device, one by one, starting with the closest one first, by initiating clock recovery (CR) followed by equalization. LT consists of AUX reads and writes transactions and the constant polling of status registers. This brings us to the problem. The time to complete LT can be over 3s.
Starting with DP version 2.1, VESA (Video Electronics Standards Association) solves this problem with 128b/132b concurrent LTTPR LT. Concurrent LT deprecates CR Done and adds Clock and Data Switch (CDS), Hop, and Intra-Hop Aux transaction to achieve faster LT.
How does all this work? The DP-TX starts by initiating CR and each downstream LTTPR PHY will drive its local clock through its DFP. The DP-RX will acknowledge the reception of CR and this propagates back to the DP-TX. The DP-TX starts equalization and the LTTPRs switch to Intra-Hop Aux mode and each Hop on the link is trained concurrently by the TPS2 training pattern. After all Hops are trained, the DP-TX will initiate CDS, DFP PHYs switch to DP-TX PHY, and DFPs exit Intra-Hop AUX mode resulting in seamless communication between the DP-TX and DP-RX. LT will finish within 650ms.
Cadence is an early adopter of this new DP feature and has a mature and proven Verification IP and TripleCheck (TC) solution. Visit the Simulation VIP page.