Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Don't lose touch with what's new in the world of SystemC! Cadence is a long time contributor and sponsor of SystemC initiatives, and that commitment continues to show during next week's SystemC Day and North American SystemC User Group (NASCUG) at DVCon. The conference is being held at the DoubleTree hotel in San Jose, California, February 28th-March 3rd. Cadence has been involved in SystemC initiatives for so long I sometimes forget that not everyone knows the extent of our involvement. You can see the evidence in next week's activities!

As a Corporate Member of the Open SystemC Initiative (OSCI), Cadence is active in leadership of the organization and funding activities. Stan Krolikoski is on the board of directors directing investment in OSCI to continue funding the standards development activities. We participate in working groups, and most recently contributed to the IEEE P1666 2011 efforts.

Cadence is a sponsor of the upcoming SystemC Day on Monday, Feb 28th, an important part of this years NASCUG 15:

NASCUG 15 with Jim Hogan Keynote

The day starts off with the NASCUG 15 (North American SystemC Users Group) meeting featuring a keynote speech by Industry expert and private investor Jim Hogan. Jim will discuss the semiconductor industry’s growing adoption of SoC design and its reliance on diverse sources of hardware and software IP, developed both internally and externally.

NASCUG also includes technical presentations on architectural modeling, verification, and analog/mixed-signal design using SystemC. An update of technical working group activities will be presented.

Agenda is now available at www.nascug.org.

DVCon Tutorial: "Software-driven Verification using TLM-2.0 Virtual Platforms”

Presenters:

• John Aynsley - Doulos
• David Black - XtremeEDA Corp.
• Bill Bunton - LSI Corp.
• Volkan Esen - Infineon Technologies
• Trevor Wieman - Intel Corp.

In addition to embedded software development, virtual platforms can effectively be deployed for software-driven verification, in which SystemC TLM-2.0 loosely-timed transaction-level platforms are connected by using transactors to signal-level representations of new subsystem hardware at the RT-level.

This tutorial will provide both a detailed technology overview of software-driven verification techniques using loosely-timed SystemC TLM-2.0 based virtual platforms, and real-world case studies describing how these techniques benefit design teams.

Steve Brown